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authorBill Wendling <isanbard@gmail.com>2010-11-10 01:07:54 +0000
committerBill Wendling <isanbard@gmail.com>2010-11-10 01:07:54 +0000
commit91607f878ce21543f3b3af94f89054167ce8ddc8 (patch)
tree695eae2ecc59db50b649f869eaac04717256cd0d /llvm/lib
parentde5c4dc24b63c0e94bb698c44a6bbdf4fc08ba5d (diff)
downloadbcm5719-llvm-91607f878ce21543f3b3af94f89054167ce8ddc8.tar.gz
bcm5719-llvm-91607f878ce21543f3b3af94f89054167ce8ddc8.zip
Emit a '!' if this is a "writeback" register or memory address.
llvm-svn: 118662
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 65f0ad4bb50..e00ced265e3 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -382,10 +382,10 @@ void ARMOperand::dump(raw_ostream &OS) const {
getImm()->print(OS);
break;
case Memory:
- OS << "<memory>";
+ OS << "<memory" << (!Mem.Writeback ? ">" : "!>");
break;
case Register:
- OS << "<register " << getReg() << ">";
+ OS << "<register " << getReg() << (!Reg.Writeback ? ">" : "!>");
break;
case RegisterList: {
OS << "<register_list ";
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