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| author | Dan Gohman <gohman@apple.com> | 2009-11-19 16:35:11 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-11-19 16:35:11 +0000 |
| commit | 91431b008b572749fba5f57f8f32a3087dbf7662 (patch) | |
| tree | c618b35a5828ae6954139585a05a50c039b7d9fe /llvm/lib | |
| parent | 1dfe1bead6a933329df9f511981f04a4257ca69a (diff) | |
| download | bcm5719-llvm-91431b008b572749fba5f57f8f32a3087dbf7662.tar.gz bcm5719-llvm-91431b008b572749fba5f57f8f32a3087dbf7662.zip | |
Fix a typo in a comment.
llvm-svn: 89360
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td index 642d10f5aa6..d396cc807e8 100644 --- a/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -44,7 +44,7 @@ class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> { let Num = num; } -// Ywo halves of 32-bit register +// Two halves of 32-bit register multiclass Rss<bits<3> group, bits<3> num, string n> { def H : Rs<group, num, 1, !strconcat(n, ".h")>; def L : Rs<group, num, 0, !strconcat(n, ".l")>; |
