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author | Sanjay Patel <spatel@rotateright.com> | 2015-07-01 17:58:53 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2015-07-01 17:58:53 +0000 |
commit | 910d5daa4bc5eebe7056391a0571499732d4b7b5 (patch) | |
tree | 404393d965a600e50872d7ea9c7840d930accdc0 /llvm/lib | |
parent | e4d95c6c9a0c66cbd4fcb148168bff2a0ed82b6c (diff) | |
download | bcm5719-llvm-910d5daa4bc5eebe7056391a0571499732d4b7b5.tar.gz bcm5719-llvm-910d5daa4bc5eebe7056391a0571499732d4b7b5.zip |
fix formatting; NFC
llvm-svn: 241175
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 5424c18ae50..c19fcdc4bb1 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -1679,7 +1679,7 @@ unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, bool WantZExt, MachineMemOperand *MMO) { - if(!TLI.allowsMisalignedMemoryAccesses(VT)) + if (!TLI.allowsMisalignedMemoryAccesses(VT)) return 0; // Simplify this down to something we can handle. @@ -1966,7 +1966,7 @@ bool AArch64FastISel::selectLoad(const Instruction *I) { bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr, MachineMemOperand *MMO) { - if(!TLI.allowsMisalignedMemoryAccesses(VT)) + if (!TLI.allowsMisalignedMemoryAccesses(VT)) return false; // Simplify this down to something we can handle. |