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| author | Craig Topper <craig.topper@intel.com> | 2018-01-06 21:02:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-06 21:02:22 +0000 |
| commit | 90353a9f42a3c99c34cbdaf7d6ea1ab47badccd2 (patch) | |
| tree | c82ece851c19a0aa031eb1fa05d57d0191981e06 /llvm/lib | |
| parent | a82eef2363c7b179ea0a343534c99dd192c7c6fd (diff) | |
| download | bcm5719-llvm-90353a9f42a3c99c34cbdaf7d6ea1ab47badccd2.tar.gz bcm5719-llvm-90353a9f42a3c99c34cbdaf7d6ea1ab47badccd2.zip | |
[X86] Remove an unnecessary VCVTTSD2SIrrb/VCVTSS2SIrrb instruction with no isel pattern that only existed for the assembler. Use VCVTTSD2SIrrb_Int instead.
For consistency use the _Int version of VCVTTSD2SIrr_Int and VCVTTSD2SIrm_Int for the assembler as well.
llvm-svn: 321944
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 50 |
1 files changed, 23 insertions, 27 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 751c954adcb..3c06ca34fa0 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6595,45 +6595,41 @@ multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC, X86VectorVTInfo _DstRC, SDNode OpNode, SDNode OpNodeRnd, OpndItins itins, string aliasStr>{ let Predicates = [HasAVX512] in { + let isCodeGenOnly = 1 in { def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))], itins.rr>, EVEX, Sched<[itins.Sched]>; - let hasSideEffects = 0 in - def rrb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), - !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), - [], itins.rr>, EVEX, EVEX_B, Sched<[itins.Sched]>; def rm : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))], itins.rm>, EVEX, Sched<[itins.Sched.Folded, ReadAfterLd]>; + } + + def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), + !strconcat(asm,"\t{$src, $dst|$dst, $src}"), + [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), + (i32 FROUND_CURRENT)))], itins.rr>, + EVEX, VEX_LIG, Sched<[itins.Sched]>; + def rrb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), + !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), + [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), + (i32 FROUND_NO_EXC)))], itins.rr>, + EVEX,VEX_LIG , EVEX_B, Sched<[itins.Sched]>; + let mayLoad = 1, hasSideEffects = 0 in + def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), + (ins _SrcRC.IntScalarMemOp:$src), + !strconcat(asm,"\t{$src, $dst|$dst, $src}"), + [], itins.rm>, EVEX, VEX_LIG, + Sched<[itins.Sched.Folded, ReadAfterLd]>; def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", - (!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>; + (!cast<Instruction>(NAME # "rr_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0>; def : InstAlias<asm # aliasStr # "\t{{sae}, $src, $dst|$dst, $src, {sae}}", - (!cast<Instruction>(NAME # "rrb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>; + (!cast<Instruction>(NAME # "rrb_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0>; def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", - (!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst, - _SrcRC.ScalarMemOp:$src), 0>; - - let isCodeGenOnly = 1 in { - def rr_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), - !strconcat(asm,"\t{$src, $dst|$dst, $src}"), - [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), - (i32 FROUND_CURRENT)))], itins.rr>, - EVEX, VEX_LIG, Sched<[itins.Sched]>; - def rrb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src), - !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), - [(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src), - (i32 FROUND_NO_EXC)))], itins.rr>, - EVEX,VEX_LIG , EVEX_B, Sched<[itins.Sched]>; - let mayLoad = 1, hasSideEffects = 0 in - def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), - (ins _SrcRC.IntScalarMemOp:$src), - !strconcat(asm,"\t{$src, $dst|$dst, $src}"), - [], itins.rm>, EVEX, VEX_LIG, - Sched<[itins.Sched.Folded, ReadAfterLd]>; - } // isCodeGenOnly = 1 + (!cast<Instruction>(NAME # "rm_Int") _DstRC.RC:$dst, + _SrcRC.IntScalarMemOp:$src), 0>; } //HasAVX512 } |
