diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-06-28 17:58:01 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-28 17:58:01 +0000 |
| commit | 90317d1d94afddb77ec5f78c8f5df4887f3e3a09 (patch) | |
| tree | 4b5314f104339e5a0ea7d253483b7c12edd94033 /llvm/lib | |
| parent | b757fc3878d90976cd7ca92291aa8b626d5dff6b (diff) | |
| download | bcm5719-llvm-90317d1d94afddb77ec5f78c8f5df4887f3e3a09.tar.gz bcm5719-llvm-90317d1d94afddb77ec5f78c8f5df4887f3e3a09.zip | |
[X86] Suppress load folding into and/or/xor if it will prevent matching btr/bts/btc.
This is a follow up to r335753. At the time I forgot about isProfitableToFold which makes this pretty easy.
Differential Revision: https://reviews.llvm.org/D48706
llvm-svn: 335895
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index e54115e532a..c7120cf3673 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -569,6 +569,35 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { return false; } + // Don't fold load if this matches the BTS/BTR/BTC patterns. + // BTS: (or X, (shl 1, n)) + // BTR: (and X, (rotl -2, n)) + // BTC: (xor X, (shl 1, n)) + if (U->getOpcode() == ISD::OR || U->getOpcode() == ISD::XOR) { + if (U->getOperand(0).getOpcode() == ISD::SHL && + isOneConstant(U->getOperand(0).getOperand(0))) + return false; + + if (U->getOperand(1).getOpcode() == ISD::SHL && + isOneConstant(U->getOperand(1).getOperand(0))) + return false; + } + if (U->getOpcode() == ISD::AND) { + SDValue U0 = U->getOperand(0); + SDValue U1 = U->getOperand(1); + if (U0.getOpcode() == ISD::ROTL) { + auto *C = dyn_cast<ConstantSDNode>(U0.getOperand(0)); + if (C && C->getSExtValue() == -2) + return false; + } + + if (U1.getOpcode() == ISD::ROTL) { + auto *C = dyn_cast<ConstantSDNode>(U1.getOperand(0)); + if (C && C->getSExtValue() == -2) + return false; + } + } + break; } case ISD::SHL: |

