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| author | Sam Parker <sam.parker@arm.com> | 2019-02-11 11:35:42 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2019-02-11 11:35:42 +0000 |
| commit | 8ff143033a7760be8a174d6b39aad269e113926a (patch) | |
| tree | 45f204ede04dafb2b4f48f8aa92e37fb325b0e0c /llvm/lib | |
| parent | ded96df01e95b4ac22e39bca45cf5e655253b1ea (diff) | |
| download | bcm5719-llvm-8ff143033a7760be8a174d6b39aad269e113926a.tar.gz bcm5719-llvm-8ff143033a7760be8a174d6b39aad269e113926a.zip | |
[ARM] Add v8m.base pattern for add negative imm
The v8m.base ISA contains movw, which can operate on an unsigned
16-bit value. Add the pattern that converts an add with a negative
value, that could fit into 16-bits when negated, into a sub with that
positive value.
Differential Revision: https://reviews.llvm.org/D57942
llvm-svn: 353692
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index f3c4915a89e..a38980cc796 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -2147,6 +2147,11 @@ def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm), (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; +// Do the same for v8m targets since they support movw with a 16-bit value. +def : T1Pat<(add tGPR:$src, imm0_65535_neg:$imm), + (tSUBrr tGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>, + Requires<[HasV8MBaseline]>; + let AddedComplexity = 1 in def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm), (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>; |
