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| author | Karthik Bhat <kv.bhat@samsung.com> | 2015-01-05 13:11:07 +0000 |
|---|---|---|
| committer | Karthik Bhat <kv.bhat@samsung.com> | 2015-01-05 13:11:07 +0000 |
| commit | 8ec742c2f9c12e463365f97d25103dc2d095d7b3 (patch) | |
| tree | d4a43bd6df4c6299555877d0fe4dda42fd76f2be /llvm/lib | |
| parent | 6ae456b0d708236fdbcaa76a50971fbd94caaeaa (diff) | |
| download | bcm5719-llvm-8ec742c2f9c12e463365f97d25103dc2d095d7b3.tar.gz bcm5719-llvm-8ec742c2f9c12e463365f97d25103dc2d095d7b3.zip | |
Select lower sub,abs pattern to sabd on AArch64
This patch lowers patterns such as-
sub v0.4s, v0.4s, v1.4s
abs v0.4s, v0.4s
to
sabd v0.4s, v0.4s, v1.4s
on AArch64.
Review: http://reviews.llvm.org/D6781
llvm-svn: 225165
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrInfo.td | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 3f1dbe0bfc0..7f914797e37 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -2733,6 +2733,33 @@ defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn", BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >; defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>; +// SABD Vd.<T>, Vn.<T>, Vm.<T> Subtracts the elements of Vm from the corresponding +// elements of Vn, and places the absolute values of the results in the elements of Vd. +def : Pat<(xor (v8i8 (AArch64vashr (v8i8(sub V64:$Rn, V64:$Rm)), (i32 7))), + (v8i8 (add (v8i8(sub V64:$Rn, V64:$Rm)), + (AArch64vashr (v8i8(sub V64:$Rn, V64:$Rm)), (i32 7))))), + (SABDv8i8 V64:$Rn, V64:$Rm)>; +def : Pat<(xor (v4i16 (AArch64vashr (v4i16(sub V64:$Rn, V64:$Rm)), (i32 15))), + (v4i16 (add (v4i16(sub V64:$Rn, V64:$Rm)), + (AArch64vashr (v4i16(sub V64:$Rn, V64:$Rm)), (i32 15))))), + (SABDv4i16 V64:$Rn, V64:$Rm)>; +def : Pat<(xor (v2i32 (AArch64vashr (v2i32(sub V64:$Rn, V64:$Rm)), (i32 31))), + (v2i32 (add (v2i32(sub V64:$Rn, V64:$Rm)), + (AArch64vashr (v2i32(sub V64:$Rn, V64:$Rm)), (i32 31))))), + (SABDv2i32 V64:$Rn, V64:$Rm)>; +def : Pat<(xor (v16i8 (AArch64vashr (v16i8(sub V128:$Rn, V128:$Rm)), (i32 7))), + (v16i8 (add (v16i8(sub V128:$Rn, V128:$Rm)), + (AArch64vashr (v16i8(sub V128:$Rn, V128:$Rm)), (i32 7))))), + (SABDv16i8 V128:$Rn, V128:$Rm)>; +def : Pat<(xor (v8i16 (AArch64vashr (v8i16(sub V128:$Rn, V128:$Rm)), (i32 15))), + (v8i16 (add (v8i16(sub V128:$Rn, V128:$Rm)), + (AArch64vashr (v8i16(sub V128:$Rn, V128:$Rm)), (i32 15))))), + (SABDv8i16 V128:$Rn, V128:$Rm)>; +def : Pat<(xor (v4i32 (AArch64vashr (v4i32(sub V128:$Rn, V128:$Rm)), (i32 31))), + (v4i32 (add (v4i32(sub V128:$Rn, V128:$Rm)), + (AArch64vashr (v4i32(sub V128:$Rn, V128:$Rm)), (i32 31))))), + (SABDv4i32 V128:$Rn, V128:$Rm)>; + def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm), (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>; def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm), |
