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authorEli Friedman <eli.friedman@gmail.com>2011-10-10 22:28:47 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-10-10 22:28:47 +0000
commit8ec0897db6d35ee756468c25157dce783324e186 (patch)
tree4e97b26d21268dc4775adc6386cf4b58982b1d15 /llvm/lib
parenta10e6c1052b90802d7da799332dbfd4a1a7b36ae (diff)
downloadbcm5719-llvm-8ec0897db6d35ee756468c25157dce783324e186.tar.gz
bcm5719-llvm-8ec0897db6d35ee756468c25157dce783324e186.zip
Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.
llvm-svn: 141585
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp16
1 files changed, 4 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 02c9f8ef228..5bd3e2b6711 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3757,12 +3757,8 @@ static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
if (!Subtarget->hasAVX())
return false;
- // Match any permutation of 128-bit vector with 64-bit types
- if (NumLanes == 1 && NumElts != 2)
- return false;
-
- // Only match 256-bit with 32 types
- if (VT.getSizeInBits() == 256 && NumElts != 4)
+ // Only match 256-bit with 64-bit types
+ if (VT.getSizeInBits() != 256 || NumElts != 4)
return false;
// The mask on the high lane is independent of the low. Both can match
@@ -3793,12 +3789,8 @@ static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
if (!Subtarget->hasAVX())
return false;
- // Match any permutation of 128-bit vector with 32-bit types
- if (NumLanes == 1 && NumElts != 4)
- return false;
-
- // Only match 256-bit with 32 types
- if (VT.getSizeInBits() == 256 && NumElts != 8)
+ // Only match 256-bit with 32-bit types
+ if (VT.getSizeInBits() != 256 || NumElts != 8)
return false;
// The mask on the high lane should be the same as the low. Actually,
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