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author | Bill Wendling <isanbard@gmail.com> | 2010-11-08 23:49:57 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2010-11-08 23:49:57 +0000 |
commit | 8d2aa03ce1385506ce74d4d0fddafad09a79dc2d (patch) | |
tree | 7ab897d94dae5db505396674a0b38f11fee55255 /llvm/lib | |
parent | fbb44c4d74ebfb2d0e3e77f0f4254cafb5ad3fd6 (diff) | |
download | bcm5719-llvm-8d2aa03ce1385506ce74d4d0fddafad09a79dc2d.tar.gz bcm5719-llvm-8d2aa03ce1385506ce74d4d0fddafad09a79dc2d.zip |
The "addRegListOperands()" function returns the start register and the total
number of registers in the list.
llvm-svn: 118456
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 36 |
1 files changed, 21 insertions, 15 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a456d3ce524..71fa27cb46f 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -221,6 +221,20 @@ public: bool isRegList() const { return Kind == RegisterList; } bool isToken() const { return Kind == Token; } bool isMemory() const { return Kind == Memory; } + bool isMemMode5() const { + if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted || + Mem.Writeback || Mem.Negative) + return false; + // If there is an offset expression, make sure it's valid. + if (!Mem.Offset) + return true; + const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset); + if (!CE) + return false; + // The offset must be a multiple of 4 in the range 0-1020. + int64_t Value = CE->getValue(); + return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); + } void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. @@ -244,26 +258,18 @@ public: Inst.addOperand(MCOperand::CreateReg(getReg())); } + void addRegListOperands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + std::pair<unsigned, unsigned> RegList = getRegList(); + Inst.addOperand(MCOperand::CreateReg(RegList.first)); + Inst.addOperand(MCOperand::CreateImm(RegList.second)); + } + void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } - bool isMemMode5() const { - if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted || - Mem.Writeback || Mem.Negative) - return false; - // If there is an offset expression, make sure it's valid. - if (!Mem.Offset) - return true; - const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset); - if (!CE) - return false; - // The offset must be a multiple of 4 in the range 0-1020. - int64_t Value = CE->getValue(); - return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); - } - void addMemMode5Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && isMemMode5() && "Invalid number of operands!"); |