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| author | Craig Topper <craig.topper@intel.com> | 2018-02-08 08:29:43 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-02-08 08:29:43 +0000 |
| commit | 8d0c8c9be158d2c83864c3124f258f8790476602 (patch) | |
| tree | 7b8e62bbb3bbfabd9d20595076b7ad8821460b9d /llvm/lib | |
| parent | 93505707b6d3ec117e555c5a48adc2cc56470e38 (diff) | |
| download | bcm5719-llvm-8d0c8c9be158d2c83864c3124f258f8790476602.tar.gz bcm5719-llvm-8d0c8c9be158d2c83864c3124f258f8790476602.zip | |
[X86] Support folding in a k-register OR when creating KORTEST from scalar compare of a bitcast from vXi1.
This should allow us to remove the kortest intrinsic from IR and use compare+bitcast+or in IR instead.
llvm-svn: 324580
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 500a1d3ab03..5aaf2417e1b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18149,7 +18149,15 @@ static SDValue EmitKTEST(SDValue Op0, SDValue Op1, ISD::CondCode CC, } else return SDValue(); - SDValue KORTEST = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, Op0, Op0); + // If the input is an OR, we can combine it's operands into the KORTEST. + SDValue LHS = Op0; + SDValue RHS = Op0; + if (Op0.getOpcode() == ISD::OR && Op0.hasOneUse( && Op0.hasOneUse())) { + LHS = Op0.getOperand(0); + RHS = Op0.getOperand(1); + } + + SDValue KORTEST = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS); return getSETCC(X86CC, KORTEST, dl, DAG); } |

