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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-05 16:56:28 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-07-05 16:56:28 +0000 |
commit | 8c3765dc6b1cc8339f3e8f42e10d0ea5b7bc8111 (patch) | |
tree | 6d61591b3f4f9f30107a19dae268ba1830ace4aa /llvm/lib | |
parent | 91c9d4251cfcde9055c9af65ef7a70ab779c61a2 (diff) | |
download | bcm5719-llvm-8c3765dc6b1cc8339f3e8f42e10d0ea5b7bc8111.tar.gz bcm5719-llvm-8c3765dc6b1cc8339f3e8f42e10d0ea5b7bc8111.zip |
[CostModel][X86] Add UDIV/UREM by pow2 costs
Normally InstCombine would have simplified these to SRL/AND instructions but we may still see these during SLP vectorization etc.
llvm-svn: 336371
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 44 |
1 files changed, 29 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index b0dff40260e..8132e77b472 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -244,25 +244,39 @@ int X86TTIImpl::getArithmeticInstrCost( } } - if (ISD == ISD::SDIV && + if ((ISD == ISD::SDIV || ISD == ISD::UDIV || ISD == ISD::UREM) && (Op2Info == TargetTransformInfo::OK_UniformConstantValue || Op2Info == TargetTransformInfo::OK_NonUniformConstantValue) && Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) { - // On X86, vector signed division by constants power-of-two are - // normally expanded to the sequence SRA + SRL + ADD + SRA. - // The OperandValue properties may not be the same as that of the previous - // operation; conservatively assume OP_None. - int Cost = 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, - Op2Info, TargetTransformInfo::OP_None, - TargetTransformInfo::OP_None); - Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, - TargetTransformInfo::OP_None, - TargetTransformInfo::OP_None); - Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, - TargetTransformInfo::OP_None, - TargetTransformInfo::OP_None); + if (ISD == ISD::SDIV) { + // On X86, vector signed division by constants power-of-two are + // normally expanded to the sequence SRA + SRL + ADD + SRA. + // The OperandValue properties may not be the same as that of the previous + // operation; conservatively assume OP_None. + int Cost = + 2 * getArithmeticInstrCost(Instruction::AShr, Ty, Op1Info, Op2Info, + TargetTransformInfo::OP_None, + TargetTransformInfo::OP_None); + Cost += getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, + TargetTransformInfo::OP_None, + TargetTransformInfo::OP_None); + Cost += getArithmeticInstrCost(Instruction::Add, Ty, Op1Info, Op2Info, + TargetTransformInfo::OP_None, + TargetTransformInfo::OP_None); + + return Cost; + } - return Cost; + // Vector unsigned division/remainder will be simplified to shifts/masks. + if (ISD == ISD::UDIV) + return getArithmeticInstrCost(Instruction::LShr, Ty, Op1Info, Op2Info, + TargetTransformInfo::OP_None, + TargetTransformInfo::OP_None); + + if (ISD == ISD::UREM) + return getArithmeticInstrCost(Instruction::And, Ty, Op1Info, Op2Info, + TargetTransformInfo::OP_None, + TargetTransformInfo::OP_None); } static const CostTblEntry AVX512BWUniformConstCostTable[] = { |