[mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter

Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with
additional flag, so instead of always lowering to lui %hi(...),
addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi,
%higher or %highest depending on the added flag.

Differential Revision: https://reviews.llvm.org/D47941

llvm-svn: 334490

3 files changed, 67 insertions, 22 deletions

diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index 66ca5faf82f..af936e6fc96 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -446,7 +446,7 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
       // operands to lowered instructions.
 
       BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
-          .addMBB(TgtMBB)
+          .addMBB(TgtMBB, MipsII::MO_ABS_HI)
           .addMBB(BalTgtMBB);
 
       MachineInstrBuilder BalInstr =
@@ -454,7 +454,7 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
       MachineInstrBuilder ADDiuInstr =
           BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
               .addReg(Mips::AT)
-              .addMBB(TgtMBB)
+              .addMBB(TgtMBB, MipsII::MO_ABS_LO)
               .addMBB(BalTgtMBB);
       if (STI->hasMips32r6()) {
         LongBrMBB->insert(Pos, ADDiuInstr);
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.cpp b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
index a4ab7d3a578..2b7f6409992 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.cpp
@@ -219,26 +219,77 @@ lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const {
   // Lower register operand.
   OutMI.addOperand(LowerOperand(MI->getOperand(0)));
 
-  // Create %hi($tgt-$baltgt).
-  OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
-                             MI->getOperand(2).getMBB(),
-                             MipsMCExpr::MEK_HI));
+  MipsMCExpr::MipsExprKind Kind;
+  unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
+  switch (TargetFlags) {
+  case MipsII::MO_HIGHEST:
+    Kind = MipsMCExpr::MEK_HIGHEST;
+    break;
+  case MipsII::MO_HIGHER:
+    Kind = MipsMCExpr::MEK_HIGHER;
+    break;
+  case MipsII::MO_ABS_HI:
+    Kind = MipsMCExpr::MEK_HI;
+    break;
+  case MipsII::MO_ABS_LO:
+    Kind = MipsMCExpr::MEK_LO;
+    break;
+  default:
+    report_fatal_error("Unexpected flags for lowerLongBranchLUi");
+  }
+
+  if (MI->getNumOperands() == 2) {
+    const MCExpr *Expr =
+        MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
+    const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+    OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+  } else if (MI->getNumOperands() == 3) {
+    // Create %hi($tgt-$baltgt).
+    OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
+                               MI->getOperand(2).getMBB(), Kind));
+  }
 }
 
-void MipsMCInstLower::lowerLongBranchADDiu(
-    const MachineInstr *MI, MCInst &OutMI, int Opcode,
-    MipsMCExpr::MipsExprKind Kind) const {
+void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
+                                           MCInst &OutMI, int Opcode) const {
   OutMI.setOpcode(Opcode);
 
+  MipsMCExpr::MipsExprKind Kind;
+  unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
+  switch (TargetFlags) {
+  case MipsII::MO_HIGHEST:
+    Kind = MipsMCExpr::MEK_HIGHEST;
+    break;
+  case MipsII::MO_HIGHER:
+    Kind = MipsMCExpr::MEK_HIGHER;
+    break;
+  case MipsII::MO_ABS_HI:
+    Kind = MipsMCExpr::MEK_HI;
+    break;
+  case MipsII::MO_ABS_LO:
+    Kind = MipsMCExpr::MEK_LO;
+    break;
+  default:
+    report_fatal_error("Unexpected flags for lowerLongBranchADDiu");
+  }
+
   // Lower two register operands.
   for (unsigned I = 0, E = 2; I != E; ++I) {
     const MachineOperand &MO = MI->getOperand(I);
     OutMI.addOperand(LowerOperand(MO));
   }
 
-  // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
-  OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
-                             MI->getOperand(3).getMBB(), Kind));
+  if (MI->getNumOperands() == 3) {
+    // Lower register operand.
+    const MCExpr *Expr =
+        MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
+    const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+    OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+  } else if (MI->getNumOperands() == 4) {
+    // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
+    OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
+                               MI->getOperand(3).getMBB(), Kind));
+  }
 }
 
 bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
@@ -250,16 +301,10 @@ bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
     lowerLongBranchLUi(MI, OutMI);
     return true;
   case Mips::LONG_BRANCH_ADDiu:
-    lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO);
+    lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
     return true;
   case Mips::LONG_BRANCH_DADDiu:
-    unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
-    if (TargetFlags == MipsII::MO_ABS_HI)
-      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_HI);
-    else if (TargetFlags == MipsII::MO_ABS_LO)
-      lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_LO);
-    else
-      report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
+    lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu);
     return true;
   }
 }
diff --git a/llvm/lib/Target/Mips/MipsMCInstLower.h b/llvm/lib/Target/Mips/MipsMCInstLower.h
index fb507964382..e19f21c9883 100644
--- a/llvm/lib/Target/Mips/MipsMCInstLower.h
+++ b/llvm/lib/Target/Mips/MipsMCInstLower.h
@@ -44,8 +44,8 @@ private:
   MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
                       MipsMCExpr::MipsExprKind Kind) const;
   void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
-  void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
-                            MipsMCExpr::MipsExprKind Kind) const;
+  void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
+                            int Opcode) const;
   bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
 };