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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-08-20 01:49:49 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-08-20 01:49:49 +0000 |
| commit | 8a675a5d09184735dfe459fa0deba1afa33f1a3d (patch) | |
| tree | a7fefc04c1622efcdcc11074aac0af685a85453b /llvm/lib | |
| parent | 7b00dc885d2fb632bafb0d72fc65db02857a25bb (diff) | |
| download | bcm5719-llvm-8a675a5d09184735dfe459fa0deba1afa33f1a3d.tar.gz bcm5719-llvm-8a675a5d09184735dfe459fa0deba1afa33f1a3d.zip | |
call computeRegisterProperties
llvm-svn: 29780
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 56d61165c3c..cf23f2a4409 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -42,11 +42,17 @@ namespace { ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) : TargetLowering(TM) { + addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass); + + //LLVM requires that a register class supports MVT::f64! + addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass); + setOperationAction(ISD::RET, MVT::Other, Custom); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); setSchedulingPreference(SchedulingForRegPressure); + computeRegisterProperties(); } namespace llvm { |
