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authorAnton Korobeynikov <asl@math.spbu.ru>2009-10-21 00:12:44 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-10-21 00:12:44 +0000
commit8a06a4e5c89066e78e5f14874028cd237e80c7e0 (patch)
tree758c375961d8f7a93e0250c13cadb95c00fb0799 /llvm/lib
parent196b0e5431668e2558609e41bad3ce447cb33b19 (diff)
downloadbcm5719-llvm-8a06a4e5c89066e78e5f14874028cd237e80c7e0.tar.gz
bcm5719-llvm-8a06a4e5c89066e78e5f14874028cd237e80c7e0.zip
Ignore all implicit reg operands
llvm-svn: 84708
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp b/llvm/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp
index e9b0c92cf4e..175b6b3f3f7 100644
--- a/llvm/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp
+++ b/llvm/lib/Target/MSP430/AsmPrinter/MSP430MCInstLower.cpp
@@ -100,6 +100,8 @@ void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
MI->dump();
assert(0 && "unknown operand type");
case MachineOperand::MO_Register:
+ // Ignore all implicit register operands.
+ if (MO.isImplicit()) continue;
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
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