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authorEvan Cheng <evan.cheng@apple.com>2007-01-29 22:23:02 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-01-29 22:23:02 +0000
commit8953edc8a584ef5693715a9768c1e49e0d181ba6 (patch)
tree53dd471f100965a41928ae26a7c93d297e4313bb /llvm/lib
parent43e8518d8bc60106950e3bc0c6359cb8c5f96175 (diff)
downloadbcm5719-llvm-8953edc8a584ef5693715a9768c1e49e0d181ba6.tar.gz
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Comment.
llvm-svn: 33633
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index 0dfd790b56d..445fb26fc00 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -97,7 +97,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
}];
// FIXME: We are reserving r12 in case the PEI needs to use it to
// generate large stack offset. Make it available once we have register
- // scavenging.
+ // scavenging. Similarly r3 is reserved in Thumb mode for now.
let MethodBodies = [{
// FP is R11, R9 is available.
static const unsigned ARM_GPR_AO_1[] = {
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