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authorVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2015-11-16 17:05:01 +0000
committerVasileios Kalintiris <Vasileios.Kalintiris@imgtec.com>2015-11-16 17:05:01 +0000
commit88faf6d6979dff876aabbec690b7096d123f3092 (patch)
treee7de1ce1e4bbef175feedfc1884ab0dbb87d2526 /llvm/lib
parented5cc95d2297f9a7c12ea6a4fd3c517c5bc9dfac (diff)
downloadbcm5719-llvm-88faf6d6979dff876aabbec690b7096d123f3092.tar.gz
bcm5719-llvm-88faf6d6979dff876aabbec690b7096d123f3092.zip
[mips] Disable code generation through FastISel for MIPS32R6.
Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14708 llvm-svn: 253225
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/MipsFastISel.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 23b0215b047..e9eaf810637 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -192,10 +192,10 @@ public:
TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext();
+ bool ISASupported = !Subtarget->hasMips32r6() && Subtarget->hasMips32();
TargetSupported =
- ((TM.getRelocationModel() == Reloc::PIC_) &&
- ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
- (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
+ ISASupported && (TM.getRelocationModel() == Reloc::PIC_) &&
+ (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32());
UnsupportedFPMode = Subtarget->isFP64bit();
}
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