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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-10 18:24:16 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-10 18:24:16 +0000 |
| commit | 8872d20788eb6a3f2bc454d1a86bdfa3b0407557 (patch) | |
| tree | 6d355b3797221d67b00b33cfa7f0cb807038641e /llvm/lib | |
| parent | 924a4921b48d34aa3ff43a58f6434f1624ffd8c5 (diff) | |
| download | bcm5719-llvm-8872d20788eb6a3f2bc454d1a86bdfa3b0407557.tar.gz bcm5719-llvm-8872d20788eb6a3f2bc454d1a86bdfa3b0407557.zip | |
[Hexagon] Adding JR class predicated call reg instructions.
llvm-svn: 223933
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 28 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonRegisterInfo.td | 8 |
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 40d30dea043..fc3da5a3425 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -1383,6 +1383,34 @@ multiclass JMPR_base<string BaseOp> { } } +let isCall = 1, hasSideEffects = 1 in +class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, + dag InputDag = (ins IntRegs:$Rs)> + : JRInst<(outs), InputDag, + !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", + "if ($Pu) callr $Rs"), + "callr $Rs"), + [], "", J_tc_2early_SLOT2> { + bits<5> Rs; + bits<2> Pu; + let isPredicated = isPred; + let isPredicatedFalse = isPredNot; + + let IClass = 0b0101; + let Inst{27-25} = 0b000; + let Inst{24-23} = !if (isPred, 0b10, 0b01); + let Inst{22} = 0; + let Inst{21} = isPredNot; + let Inst{9-8} = !if (isPred, Pu, 0b00); + let Inst{20-16} = Rs; + + } + +let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in { + def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>; + def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>; +} + let isTerminator = 1, hasSideEffects = 0 in { let isBranch = 1 in defm JMP : JMP_base<"JMP">, PredNewRel; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index 82b417ebbf7..a7646dc7cc3 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -145,6 +145,14 @@ def CRRegs : RegisterClass<"Hexagon", [i32], 32, let Size = 32; } +def VolatileV3 { + list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7, + R28, R31, + P0, P1, P2, P3, + M0, M1, + LC0, LC1, SA0, SA1, USR_OVF]; +} + def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), [{ return isPositiveHalfWord(N); |

