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| author | Chris Lattner <sabre@nondot.org> | 2006-03-07 04:42:59 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-07 04:42:59 +0000 |
| commit | 883cefc656dc1a7e519c5559d3ddfc48bb51bdb1 (patch) | |
| tree | 18a79d0b59eed2f97504fbd588a381ee53f4a786 /llvm/lib | |
| parent | 46d6e17fe9bc01a5a8b47c735d38b4c694c2fb3a (diff) | |
| download | bcm5719-llvm-883cefc656dc1a7e519c5559d3ddfc48bb51bdb1.tar.gz bcm5719-llvm-883cefc656dc1a7e519c5559d3ddfc48bb51bdb1.zip | |
add a note
llvm-svn: 26585
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/README.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/README.txt b/llvm/lib/Target/PowerPC/README.txt index 050f6142912..8fad506f5cc 100644 --- a/llvm/lib/Target/PowerPC/README.txt +++ b/llvm/lib/Target/PowerPC/README.txt @@ -452,3 +452,17 @@ _test: srwi r3, r2, 24 blr +===-------------------------------------------------------------------------=== + +On the G5, logical CR operations are more expensive in their three +address form: ops that read/write the same register are half as expensive as +those that read from two registers that are different from their destination. + +We should model this with two separate instructions. The isel should generate +the "two address" form of the instructions. When the register allocator +detects that it needs to insert a copy due to the two-addresness of the CR +logical op, it will invoke PPCInstrInfo::convertToThreeAddress. At this point +we can convert to the "three address" instruction, to save code space. + +This only matters when we start generating cr logical ops. + |
