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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:06:30 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:06:30 +0000 |
| commit | 86c3c794faebfa5eb95968672dfd1664b8aa91bf (patch) | |
| tree | 83ec6e195d46cd61fecb4985e826bd5a6d420512 /llvm/lib | |
| parent | 8368b3b3df90e091c29688d3f115f18b309e7a73 (diff) | |
| download | bcm5719-llvm-86c3c794faebfa5eb95968672dfd1664b8aa91bf.tar.gz bcm5719-llvm-86c3c794faebfa5eb95968672dfd1664b8aa91bf.zip | |
[mips] Transfer kill flag to the newly created operand.
llvm-svn: 192662
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index f69a2d48b24..8c0991eed8e 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -768,13 +768,17 @@ static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, // Insert instruction "teq $divisor_reg, $zero, 7". MachineBasicBlock::iterator I(MI); MachineInstrBuilder MIB; + MachineOperand &Divisor = MI->getOperand(2); MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) - .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7); + .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) + .addReg(Mips::ZERO).addImm(7); // Use the 32-bit sub-register if this is a 64-bit division. if (Is64Bit) MIB->getOperand(0).setSubReg(Mips::sub_32); + // Clear Divisor's kill flag. + Divisor.setIsKill(false); return &MBB; } |

