diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-07 13:55:53 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-04-07 13:55:53 +0000 |
| commit | 85f34a56829f79cb377f3d84a5842cef60667ba7 (patch) | |
| tree | 238f3ea7a15cd9cc1d61a14137af946435868100 /llvm/lib | |
| parent | a7abda39894a8669b4aa05bd35dfced76fa8a3c6 (diff) | |
| download | bcm5719-llvm-85f34a56829f79cb377f3d84a5842cef60667ba7.tar.gz bcm5719-llvm-85f34a56829f79cb377f3d84a5842cef60667ba7.zip | |
Yea, it wasn't happy
llvm-svn: 21132
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index c3b9c1fd51d..6c3a87a2ac6 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1136,6 +1136,7 @@ unsigned ISel::SelectExpr(SDOperand N) { Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2); + return Result; case ISD::MULHS: { //MULHU - Ra<63>*Rb - Rb<63>*Ra |
