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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-18 21:43:53 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-18 21:43:53 +0000 |
| commit | 8374720aad7cee5e157e811652aa99090e396150 (patch) | |
| tree | eff6785f506e2739b7335611b9bb969ce1ed2a6a /llvm/lib | |
| parent | adf732cfbcf2b8c0f1e53b7cd139e8954e0231d9 (diff) | |
| download | bcm5719-llvm-8374720aad7cee5e157e811652aa99090e396150.tar.gz bcm5719-llvm-8374720aad7cee5e157e811652aa99090e396150.zip | |
R600/SI: Fix crash with VSELECT
https://bugs.freedesktop.org/show_bug.cgi?id=66175
llvm-svn: 186616
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 3 |
2 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 6cae978e99c..316567cef46 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -34,6 +34,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass); addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); + addRegisterClass(MVT::v2i1, &AMDGPU::VReg_64RegClass); + addRegisterClass(MVT::v4i1, &AMDGPU::VReg_128RegClass); + addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass); addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); @@ -72,6 +75,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + setOperationAction(ISD::SETCC, MVT::v2i1, Expand); + setOperationAction(ISD::SETCC, MVT::v4i1, Expand); + setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); @@ -318,7 +324,10 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( } EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { - return MVT::i1; + if (!VT.isVector()) { + return MVT::i1; + } + return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements()); } MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const { diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index c7d97c9d323..789a5187e49 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1487,6 +1487,9 @@ def : BitConvert <f64, i64, VReg_64>; def : BitConvert <v2f32, v2i32, VReg_64>; def : BitConvert <v2i32, v2f32, VReg_64>; +def : BitConvert <v4f32, v4i32, VReg_128>; +def : BitConvert <v4i32, v4f32, VReg_128>; + /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ |
