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| author | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:56 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2014-08-18 17:55:56 +0000 |
| commit | 81db56d93112a1dee0e08c6c51383db640e62030 (patch) | |
| tree | 37215741cfe1bab168d5a62278c14c4b34a988f1 /llvm/lib | |
| parent | c13c50e0f3da0898175c2f0ba752299d3cca7261 (diff) | |
| download | bcm5719-llvm-81db56d93112a1dee0e08c6c51383db640e62030.tar.gz bcm5719-llvm-81db56d93112a1dee0e08c6c51383db640e62030.zip | |
[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point XMM and YMM instructions.
Sub-group: Logic instructions.
<rdar://problem/15607571>
llvm-svn: 215922
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 99903006f20..a1bb64d8f3a 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -2097,4 +2097,13 @@ def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> { } def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>; +//-- Logic instructions --// + +// AND, ANDN, OR, XOR PS/PD. +// x,x / v,v,v. +def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>; +// x,m / v,v,m. +def : InstRW<[WriteP5Ld, ReadAfterLd], + (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>; + } // SchedModel |
