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authorMarina Yatsina <marina.yatsina@intel.com>2018-01-22 15:31:05 +0000
committerMarina Yatsina <marina.yatsina@intel.com>2018-01-22 15:31:05 +0000
commit811523cc08b5b17768ff9427691dfb70a068dbbf (patch)
tree7e8e967829e1e091f74d2e9c3796b9dead393ec7 /llvm/lib
parent7ab96f534c0ce659fa14a4a03b3345a52fa2b697 (diff)
downloadbcm5719-llvm-811523cc08b5b17768ff9427691dfb70a068dbbf.tar.gz
bcm5719-llvm-811523cc08b5b17768ff9427691dfb70a068dbbf.zip
Fix bug in commit 323096 exposed by test in test-suite-verify-machineinstrs-x86_64h-O3
Change-Id: I0a4b10d0d6c8de606d989c567ec07944ae283a87 llvm-svn: 323126
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86InstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 910e88cc59f..de1a3b47970 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -8336,7 +8336,7 @@ void X86InstrInfo::breakPartialRegDependency(
// Using XOR32rr because it has shorter encoding and zeros up the upper bits
// as well.
unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
- BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
+ BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
.addReg(XReg, RegState::Undef)
.addReg(XReg, RegState::Undef)
.addReg(Reg, RegState::ImplicitDefine);
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