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author | Michael Bedy <mjbedy@gmail.com> | 2018-03-11 03:27:50 +0000 |
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committer | Michael Bedy <mjbedy@gmail.com> | 2018-03-11 03:27:50 +0000 |
commit | 80cf9ff5642277898fb2e968a42b53e77d4bab0e (patch) | |
tree | 566edb35050b02805ad530a1f795b0088737e2d9 /llvm/lib | |
parent | 3a89be1b25e0e8a9ad760bcb469fa1fb832aef9c (diff) | |
download | bcm5719-llvm-80cf9ff5642277898fb2e968a42b53e77d4bab0e.tar.gz bcm5719-llvm-80cf9ff5642277898fb2e968a42b53e77d4bab0e.zip |
Test commit - change comment slightly.
llvm-svn: 327234
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index cf7676b46b1..68f2aa3f1ba 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -739,8 +739,8 @@ SIPeepholeSDWA::matchSDWAOperand(MachineInstr &MI) { // TODO: add support for non-SDWA instructions as OtherInst. // For now this only works with SDWA instructions. For regular instructions - // there is no way to determine if instruction write only 8/16/24-bit out of - // full register size and all registers are at min 32-bit wide. + // there is no way to determine if the instruction writes only 8/16/24-bit + // out of full register size and all registers are at min 32-bit wide. if (!TII->isSDWA(*OtherInst)) break; |