diff options
| author | Craig Topper <craig.topper@gmail.com> | 2016-11-26 02:14:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-11-26 02:14:00 +0000 |
| commit | 7f76c23781fa15458949ee2ea807b6e896788fc6 (patch) | |
| tree | 50fb6d6ed20245000c84edbfa01305e2ab89a990 /llvm/lib | |
| parent | 516fd7abfe8a8eb770e59e0f668d5a58ed4b66b6 (diff) | |
| download | bcm5719-llvm-7f76c23781fa15458949ee2ea807b6e896788fc6.tar.gz bcm5719-llvm-7f76c23781fa15458949ee2ea807b6e896788fc6.zip | |
[X86][XOP] Add a reversed reg/reg form for VPROT instructions.
The W bit distinquishes which operand is the memory operand. But if the mod bits are 3 then the memory operand is a register and there are two possible encodings. We already did this correctly for several other XOP instructions.
llvm-svn: 287961
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrXOP.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrXOP.td b/llvm/lib/Target/X86/X86InstrXOP.td index b9601642747..2b296e1e5b8 100644 --- a/llvm/lib/Target/X86/X86InstrXOP.td +++ b/llvm/lib/Target/X86/X86InstrXOP.td @@ -105,6 +105,13 @@ multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode, (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), (vt128 VR128:$src2))))]>, XOP, Sched<[WriteVarVecShift, ReadAfterLd]>; + // For disassembler + let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in + def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR128:$src2), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, + XOP_4V, VEX_W, Sched<[WriteVarVecShift]>; } let ExeDomain = SSEPackedInt in { |
