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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-03-09 13:28:37 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2017-03-09 13:28:37 +0000 |
| commit | 7f1a982d3dcf8c06036f6fb6e736eccdc2f2255c (patch) | |
| tree | f3cc522e3c7f34dc8b238abb2780c985f532bd6b /llvm/lib | |
| parent | 8bd7f3c0a5ddb45c9d9d649f600f2b348635ee9c (diff) | |
| download | bcm5719-llvm-7f1a982d3dcf8c06036f6fb6e736eccdc2f2255c.tar.gz bcm5719-llvm-7f1a982d3dcf8c06036f6fb6e736eccdc2f2255c.zip | |
[ARM] remove FIXMEs and add vcmp MC test
Minor cleanup in ARMInstrVFP.td: removed some FIXMEs and added a MC test for
vcmp that was actually missing.
Differential Revision: https://reviews.llvm.org/D30745
llvm-svn: 297376
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrVFP.td | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 794b4d2fbc8..6aa5cfffc49 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -532,8 +532,6 @@ def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0, IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm", []>; - -// FIXME: Verify encoding after integrated assembler is working. def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$Dd, DPR:$Dm), IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", @@ -606,7 +604,6 @@ def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0, let Inst{5} = 0; } -// FIXME: Verify encoding after integrated assembler is working. def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$Dd), IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", @@ -680,7 +677,6 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, // Between half, single and double-precision. For disassembly only. -// FIXME: Verify encoding after integrated assembler is working. def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>, @@ -1513,7 +1509,6 @@ def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001, // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. let Uses = [FPSCR] in { -// FIXME: Verify encoding after integrated assembler is working. def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, (outs SPR:$Sd), (ins DPR:$Dm), IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm", |
