Move code around to prepare for moving some of the logic together to another function

llvm-svn: 113267

1 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index aef02a81f41..9d507d349de 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -5271,9 +5271,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
   MachineFunction &MF = DAG.getMachineFunction();
   bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
 
-  if (isZeroShuffle(SVOp))
-    return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
-
   // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove
   // the check or come up with another solution when all MMX move to intrinsics,
   // but don't allow this to be considered legal, we don't want vector_shuffle
@@ -5281,6 +5278,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
   if (isMMX && SVOp->isSplat())
     return Op;
 
+  if (isZeroShuffle(SVOp))
+    return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
+
   // Promote splats to v4f32.
   if (SVOp->isSplat())
     return PromoteSplat(SVOp, DAG);