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| author | Akira Hatanaka <ahatanaka@mips.com> | 2011-09-30 18:51:46 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2011-09-30 18:51:46 +0000 |
| commit | 7ba8a8d656b4ef9413bd8b41274eeda06897dc37 (patch) | |
| tree | 642e2977efdb54cb8069ccfb5e3845758cdaf8e8 /llvm/lib | |
| parent | 24ff8346713d1ff9b5fbdf27dcc6e131846c68ed (diff) | |
| download | bcm5719-llvm-7ba8a8d656b4ef9413bd8b41274eeda06897dc37.tar.gz bcm5719-llvm-7ba8a8d656b4ef9413bd8b41274eeda06897dc37.zip | |
Add definitions of Mips64 rotate instructions.
llvm-svn: 140870
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 4 |
2 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index c500c1a8fe0..6d89a0e47ba 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -116,4 +116,22 @@ def DSRL32 : LogicR_shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl, imm32_63>; def DSRA32 : LogicR_shift_rotate_imm64<0x3f, 0x00, "dsra32", sra, imm32_63>; def DSLLV : LogicR_shift_rotate_reg64<0x24, 0x00, "dsllv", shl>; def DSRLV : LogicR_shift_rotate_reg64<0x26, 0x00, "dsrlv", srl>; -def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>;
\ No newline at end of file +def DSRAV : LogicR_shift_rotate_reg64<0x27, 0x00, "dsrav", sra>; + +// Rotate Instructions +let Predicates = [HasMips64r2] in { + def DROTR : LogicR_shift_rotate_imm64<0x3a, 0x01, "drotr", rotr, immZExt5>; + def DROTR32 : LogicR_shift_rotate_imm64<0x3e, 0x01, "drotr32", rotr, + imm32_63>; + def DROTRV : LogicR_shift_rotate_reg64<0x16, 0x01, "drotrv", rotr>; +} + +//===----------------------------------------------------------------------===// +// Arbitrary patterns that map to one or more instructions +//===----------------------------------------------------------------------===// + +// Small immediates +def : Pat<(i64 immSExt16:$in), + (DADDiu ZERO_64, imm:$in)>; +def : Pat<(i64 immZExt16:$in), + (DORi ZERO_64, imm:$in)>; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 4578d224b67..45f00aeb5bb 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -149,10 +149,14 @@ MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::CTPOP, MVT::i32, Expand); setOperationAction(ISD::CTTZ, MVT::i32, Expand); setOperationAction(ISD::ROTL, MVT::i32, Expand); + setOperationAction(ISD::ROTL, MVT::i64, Expand); if (!Subtarget->hasMips32r2()) setOperationAction(ISD::ROTR, MVT::i32, Expand); + if (!Subtarget->hasMips64r2()) + setOperationAction(ISD::ROTR, MVT::i64, Expand); + setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); |
