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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-13 17:52:39 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-08-13 17:52:39 +0000 |
| commit | 7b77b14198b4d1ab1847e792507ce465921bb8cd (patch) | |
| tree | 16d2ff4fb694296c550b67599429b9dd9444e354 /llvm/lib | |
| parent | ce4ddbe96061b932e6f82a8fb6686c885332d26d (diff) | |
| download | bcm5719-llvm-7b77b14198b4d1ab1847e792507ce465921bb8cd.tar.gz bcm5719-llvm-7b77b14198b4d1ab1847e792507ce465921bb8cd.zip | |
[X86][BtVer2] Use NoSchedPredicate to model default transitions in variant scheduling classes. NFC.
llvm-svn: 339589
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 1c509c72fe8..b64f3b6d0ca 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -599,14 +599,14 @@ def JWriteZeroLatency : SchedWriteRes<[]> { def JWriteZeroIdiom : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteALU]> + SchedVar<NoSchedPred, [WriteALU]> ]>; def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr, XOR32rr, XOR64rr)>; def JWriteFZeroIdiom : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]> + SchedVar<NoSchedPred, [WriteFLogic]> ]>; def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr, ANDNPSrr, VANDNPSrr, @@ -614,20 +614,20 @@ def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr, def JWriteVZeroIdiomLogic : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]> + SchedVar<NoSchedPred, [WriteVecLogic]> ]>; def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>; def JWriteVZeroIdiomLogicX : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]> + SchedVar<NoSchedPred, [WriteVecLogicX]> ]>; def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, PANDNrr, VPANDNrr)>; def JWriteVZeroIdiomALU : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]> + SchedVar<NoSchedPred, [WriteVecALU]> ]>; def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr, MMX_PSUBQirr, MMX_PSUBWirr, @@ -636,7 +636,7 @@ def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr, def JWriteVZeroIdiomALUX : SchedWriteVariant<[ SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]> + SchedVar<NoSchedPred, [WriteVecALUX]> ]>; def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, PSUBDrr, VPSUBDrr, @@ -667,8 +667,8 @@ def JSlowLEAPredicate : MCSchedPredicate< >; def JWriteLEA : SchedWriteVariant<[ - SchedVar<JSlowLEAPredicate, [JWrite3OpsLEA]>, - SchedVar<MCSchedPredicate<TruePred>, [WriteLEA]> + SchedVar<JSlowLEAPredicate, [JWrite3OpsLEA]>, + SchedVar<NoSchedPred, [WriteLEA]> ]>; def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>; |
