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| author | Chris Lattner <sabre@nondot.org> | 2010-11-16 00:57:32 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-11-16 00:57:32 +0000 |
| commit | 7b25d6fd5230cb14aa2ce286798da69c76112fbd (patch) | |
| tree | 9179ec6f05d23dd670bb0fee3cc6b5610c4d9e14 /llvm/lib | |
| parent | 73716a600a4d6d7b39d422f3e21b70e8f35ea3b9 (diff) | |
| download | bcm5719-llvm-7b25d6fd5230cb14aa2ce286798da69c76112fbd.tar.gz bcm5719-llvm-7b25d6fd5230cb14aa2ce286798da69c76112fbd.zip | |
add copy of comment to the code that will survive the mcjit'ization
llvm-svn: 119308
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp index b4a1b19d8a1..f286b27d5d1 100644 --- a/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/PPCMCCodeEmitter.cpp @@ -199,6 +199,8 @@ unsigned PPCMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const { if (MO.isReg()) { + // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. + // The GPR operand should come through here though. assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); return PPCRegisterInfo::getRegisterNumbering(MO.getReg()); |
