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| author | Sean Callanan <scallanan@apple.com> | 2009-09-15 21:43:27 +0000 |
|---|---|---|
| committer | Sean Callanan <scallanan@apple.com> | 2009-09-15 21:43:27 +0000 |
| commit | 7a27b9342c696c8b88e78378f53cca2c1e254473 (patch) | |
| tree | 26cd3a70e4805ea5b038e1e78a766bd22e9a51cf /llvm/lib | |
| parent | c8bfc466f38c39f63515a05c85987b73d7ccc04d (diff) | |
| download | bcm5719-llvm-7a27b9342c696c8b88e78378f53cca2c1e254473.tar.gz bcm5719-llvm-7a27b9342c696c8b88e78378f53cca2c1e254473.zip | |
Updated comments per Eli's suggestion.
llvm-svn: 81923
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr64bit.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index 152cf2da158..dc98a2e3099 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -458,7 +458,8 @@ def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem: [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition +// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but +// differently encoded. def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "add{l}\t{$src2, $dst|$dst, $src2}", []>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 923e2c2a4d0..66bfdcdb34a 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2428,7 +2428,8 @@ def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))), (implicit EFLAGS)]>; -// Register-Register Addition +// Register-Register Addition - Equivalent to the normal rr forms (ADD8rr, +// ADD16rr, and ADD32rr), but differently encoded. def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2), "add{b}\t{$src2, $dst|$dst, $src2}", []>; def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), |
