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| author | NAKAMURA Takumi <geek4civic@gmail.com> | 2013-11-14 04:05:22 +0000 |
|---|---|---|
| committer | NAKAMURA Takumi <geek4civic@gmail.com> | 2013-11-14 04:05:22 +0000 |
| commit | 78e80cd17d8a15c53a556a0e8f93b19289131a70 (patch) | |
| tree | 84f3b7aa16f001e3713c0a5aeb3c53783dccdee0 /llvm/lib | |
| parent | caac85e612fa6f1c1948c15a2eefe9a6ac21378e (diff) | |
| download | bcm5719-llvm-78e80cd17d8a15c53a556a0e8f93b19289131a70.tar.gz bcm5719-llvm-78e80cd17d8a15c53a556a0e8f93b19289131a70.zip | |
Whitespace.
llvm-svn: 194661
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIFixSGPRCopies.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp index 655db5b01da..446a9f7b791 100644 --- a/llvm/lib/Target/R600/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/R600/SIFixSGPRCopies.cpp @@ -23,9 +23,9 @@ /// %vreg3 <vsrc> = COPY %vreg2 <vgpr> /// BB2: /// %vreg4 <vsrc> = PHI %vreg1 <vsrc>, <BB#0>, %vreg3 <vrsc>, <BB#1> -/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc> +/// %vreg5 <vgpr> = VECTOR_INST %vreg4 <vsrc> +/// /// -/// /// The coalescer will begin at BB0 and eliminate its copy, then the resulting /// code will look like this: /// @@ -43,7 +43,7 @@ /// Now that the result of the PHI instruction is an SGPR, the register /// allocator is now forced to constrain the register class of %vreg3 to /// <sgpr> so we end up with final code like this: -/// +/// /// BB0: /// %vreg0 <sgpr> = SCALAR_INST /// ... @@ -55,7 +55,7 @@ /// %vreg4 <sgpr> = PHI %vreg0 <sgpr>, <BB#0>, %vreg3 <sgpr>, <BB#1> /// %vreg5 <vgpr> = VECTOR_INST %vreg4 <sgpr> /// -/// Now this code contains an illegal copy from a VGPR to an SGPR. +/// Now this code contains an illegal copy from a VGPR to an SGPR. /// /// In order to avoid this problem, this pass searches for PHI instructions /// which define a <vsrc> register and constrains its definition class to |
