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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-25 21:28:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-03-25 21:28:53 +0000 |
| commit | 77bf2e3704c4b1f27804d5bc08836cd0a3d8486f (patch) | |
| tree | c7361fa1e6d18b63e3c4e2a94546f183e6ca860c /llvm/lib | |
| parent | b008b37b617ba1ccc3f54edcd6aa9406e50d0f3f (diff) | |
| download | bcm5719-llvm-77bf2e3704c4b1f27804d5bc08836cd0a3d8486f.tar.gz bcm5719-llvm-77bf2e3704c4b1f27804d5bc08836cd0a3d8486f.zip | |
AMDGPU: Remove unnecessary check for isFullCopy
Subregister indexes are not used for physical register operands, so
isFullCopy is implied by the physical register check.
llvm-svn: 356956
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index bc30b29a396..21eecb1007f 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -76,7 +76,7 @@ static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) { } static bool isFullExecCopy(const MachineInstr& MI) { - return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC; + return MI.getOperand(1).getReg() == AMDGPU::EXEC; } static unsigned getOrNonExecReg(const MachineInstr &MI, |
