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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 11:22:10 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-08-02 11:22:10 +0000 |
| commit | 77558b7d13488fb0766475bc59c7a79b69741cfd (patch) | |
| tree | 4b3e23d79c5733396248e539453c532db60333ca /llvm/lib | |
| parent | 68b38866786033b17d71d8b93b0c10c8c3d3cc9b (diff) | |
| download | bcm5719-llvm-77558b7d13488fb0766475bc59c7a79b69741cfd.tar.gz bcm5719-llvm-77558b7d13488fb0766475bc59c7a79b69741cfd.zip | |
More SPU v2f32 stuff added: insertelement and shuffle.
llvm-svn: 110038
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.td | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 83726f2ea54..3a945ceedbf 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1624,6 +1624,7 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); } + case MVT::v2f32: case MVT::v2i32: { return SDValue(); } diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td index 96b0d5070b0..803ce567dc4 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td @@ -1584,6 +1584,9 @@ def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)), def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)), (ORv4f32_f32 R32FP:$rA)>; +def : Pat<(v2f32 (SPUprefslot2vec R32FP:$rA)), + (ORv4f32_f32 R32FP:$rA)>; + def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)), (ORv2f64_f64 R64FP:$rA)>; @@ -1608,6 +1611,9 @@ def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)), def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)), (ORf32_v4f32 VECREG:$rA)>; +def : Pat<(SPUvec2prefslot (v2f32 VECREG:$rA)), + (ORf32_v4f32 VECREG:$rA)>; + def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)), (ORf64_v2f64 VECREG:$rA)>; @@ -2150,6 +2156,8 @@ multiclass ShuffleBytes def v4f32 : SHUFBVecInst<v4f32, v16i8>; def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>; + def v2f32 : SHUFBVecInst<v2f32, v16i8>; + def v2f32_m32 : SHUFBVecInst<v2f32, v4i32>; def v2f64 : SHUFBVecInst<v2f64, v16i8>; def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>; |
