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| author | Marina Yatsina <marina.yatsina@intel.com> | 2016-09-28 15:52:56 +0000 |
|---|---|---|
| committer | Marina Yatsina <marina.yatsina@intel.com> | 2016-09-28 15:52:56 +0000 |
| commit | 76bfc6670b08c1ae87136a2a1c9994386b0e630e (patch) | |
| tree | cac221107fc84aa2b0442c13e7e54c1bd9a4fbf7 /llvm/lib | |
| parent | e17e055b75de5d084eee64ecba2111bde629a519 (diff) | |
| download | bcm5719-llvm-76bfc6670b08c1ae87136a2a1c9994386b0e630e.tar.gz bcm5719-llvm-76bfc6670b08c1ae87136a2a1c9994386b0e630e.zip | |
[x86] Accept 'retn' as an alias to 'ret[lqw]'\'ret' (At&t\Intel)
Implement 'retn' simply by aliasing it to the relevant 'ret' instruction
Commit on behalf of coby
Differential Revision: https://reviews.llvm.org/D24346
llvm-svn: 282601
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index f2474df7130..3cbcfa6c723 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2630,6 +2630,12 @@ def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; +// Apply 'ret' behavior to 'retn' +def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; +def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; +def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; +def : MnemonicAlias<"retn", "ret", "intel">; + def : MnemonicAlias<"sal", "shl", "intel">; def : MnemonicAlias<"salb", "shlb", "att">; def : MnemonicAlias<"salw", "shlw", "att">; |
