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| author | Changpeng Fang <changpeng.fang@gmail.com> | 2016-08-24 20:35:23 +0000 |
|---|---|---|
| committer | Changpeng Fang <changpeng.fang@gmail.com> | 2016-08-24 20:35:23 +0000 |
| commit | 75f0968b3965806cdbad375d17723c29a752fb2d (patch) | |
| tree | 048e9a4a3f42b8c559b20e63f56516b5da2efd1f /llvm/lib | |
| parent | 5f45722b036297388175ea34312b41ebb5bdb7ac (diff) | |
| download | bcm5719-llvm-75f0968b3965806cdbad375d17723c29a752fb2d.tar.gz bcm5719-llvm-75f0968b3965806cdbad375d17723c29a752fb2d.zip | |
AMDGCN/SI: Implement readlane/readfirstlane intrinsics
Summary:
This patch implements readlane/readfirstlane intrinsics.
TODO: need to define a new register class to consider the case
that the source could be a vector register or M0.
Reviewed by:
arsenm and tstellarAMD
Differential Revision:
http://reviews.llvm.org/D22489
llvm-svn: 279660
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 8e0fc856109..11400e9e675 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1066,9 +1066,9 @@ let Uses = [EXEC] in { def V_READFIRSTLANE_B32 : VOP1 < 0x00000002, (outs SReg_32:$vdst), - (ins VS_32:$src0), + (ins VGPR_32:$src0), "v_readfirstlane_b32 $vdst, $src0", - [] + [(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))] > { let isConvergent = 1; } @@ -1447,8 +1447,9 @@ defm V_READLANE_B32 : VOP2SI_3VI_m < vop3 <0x001, 0x289>, "v_readlane_b32", (outs SReg_32:$vdst), - (ins VS_32:$src0, SCSrc_32:$src1), - "v_readlane_b32 $vdst, $src0, $src1" + (ins VGPR_32:$src0, SCSrc_32:$src1), + "v_readlane_b32 $vdst, $src0, $src1", + [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))] >; defm V_WRITELANE_B32 : VOP2SI_3VI_m < |
