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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-11 22:47:06 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-02-11 22:47:06 +0000 |
| commit | 755d9127f580c3de6f5043f4cbef30bccac22834 (patch) | |
| tree | 6e380650a52f4db844409f7995e92f3467fa3164 /llvm/lib | |
| parent | 437d64c49e92ce5503cb0b682cd2c84bce571642 (diff) | |
| download | bcm5719-llvm-755d9127f580c3de6f5043f4cbef30bccac22834.tar.gz bcm5719-llvm-755d9127f580c3de6f5043f4cbef30bccac22834.zip | |
[X86][SSE] Use VSEXT/VZEXT constant folding for SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG
Preparatory step for PR31712
llvm-svn: 294874
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 474a8a60b9b..e7417b75ae7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1698,6 +1698,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setTargetDAGCombine(ISD::ANY_EXTEND); setTargetDAGCombine(ISD::SIGN_EXTEND); setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); + setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG); + setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG); setTargetDAGCombine(ISD::SINT_TO_FP); setTargetDAGCombine(ISD::UINT_TO_FP); setTargetDAGCombine(ISD::SETCC); @@ -34019,7 +34021,8 @@ static SDValue combineVSZext(SDNode *N, SelectionDAG &DAG, if (getTargetConstantBitsFromNode(Op, OpEltSizeInBits, UndefElts, EltBits)) { SmallBitVector Undefs(NumElts, false); SmallVector<APInt, 4> Vals(NumElts, APInt(EltSizeInBits, 0)); - bool IsZEXT = (Opcode == X86ISD::VZEXT); + bool IsZEXT = + (Opcode == X86ISD::VZEXT) || (Opcode == ISD::ZERO_EXTEND_VECTOR_INREG); for (unsigned i = 0; i != NumElts; ++i) { if (UndefElts[i]) { Undefs[i] = true; @@ -34311,6 +34314,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, case X86ISD::VSHLI: case X86ISD::VSRAI: case X86ISD::VSRLI: return combineVectorShift(N, DAG, DCI, Subtarget); + case ISD::SIGN_EXTEND_VECTOR_INREG: + case ISD::ZERO_EXTEND_VECTOR_INREG: case X86ISD::VSEXT: case X86ISD::VZEXT: return combineVSZext(N, DAG, DCI, Subtarget); case X86ISD::PINSRB: |
