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| author | Craig Topper <craig.topper@intel.com> | 2017-12-21 20:45:13 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-21 20:45:13 +0000 |
| commit | 742ac98d013b77569645134441ffb05ff66052bd (patch) | |
| tree | f9ba6935ee10a0c8c8ea506e65f80de8673a5798 /llvm/lib | |
| parent | df898cc5edd5e87acbd2b0eacc62b29d347b1f97 (diff) | |
| download | bcm5719-llvm-742ac98d013b77569645134441ffb05ff66052bd.tar.gz bcm5719-llvm-742ac98d013b77569645134441ffb05ff66052bd.zip | |
[X86] When lowering truncates to vXi1, don't sign extend i16/i8 types to 512-bit if we have VLX.
This should only affect what we do for v8i16. Previously we went to v8i64, but if we have VLX we only need v8i32. This prevents an unnecessary zmm usage.
llvm-svn: 321303
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 2c1bbfe1350..3150c15afe5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -16449,7 +16449,8 @@ static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG, assert((InVT.is256BitVector() || InVT.is128BitVector()) && "Unexpected vector type."); unsigned NumElts = InVT.getVectorNumElements(); - MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(512/NumElts), NumElts); + MVT EltVT = Subtarget.hasVLX() ? MVT::i32 : MVT::getIntegerVT(512/NumElts); + MVT ExtVT = MVT::getVectorVT(EltVT, NumElts); In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In); InVT = ExtVT; ShiftInx = InVT.getScalarSizeInBits() - 1; |
