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| author | Dan Gohman <gohman@apple.com> | 2008-08-22 19:19:31 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-22 19:19:31 +0000 |
| commit | 736779f0882e917b1cc2408519a2d2e8360c8c4a (patch) | |
| tree | df61408fdf6651e2cb130dbdc184642e39f76d6a /llvm/lib | |
| parent | f6c5308cabc98ede18d4d2455b3d0bd4f54942ab (diff) | |
| download | bcm5719-llvm-736779f0882e917b1cc2408519a2d2e8360c8c4a.tar.gz bcm5719-llvm-736779f0882e917b1cc2408519a2d2e8360c8c4a.zip | |
Anyext tweaks for x86. When extloading a value to i32 or i64, choose
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.
llvm-svn: 55190
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr64bit.td | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 21 |
2 files changed, 16 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86Instr64bit.td b/llvm/lib/Target/X86/X86Instr64bit.td index 5e7c73c0baa..446cfda8f64 100644 --- a/llvm/lib/Target/X86/X86Instr64bit.td +++ b/llvm/lib/Target/X86/X86Instr64bit.td @@ -1254,15 +1254,9 @@ def : Pat<(i64 (zext GR32:$src)), def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; // extload -def : Pat<(extloadi64i1 addr:$src), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src), - x86_subreg_8bit)>; -def : Pat<(extloadi64i8 addr:$src), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src), - x86_subreg_8bit)>; -def : Pat<(extloadi64i16 addr:$src), - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV16rm addr:$src), - x86_subreg_16bit)>; +def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; +def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; +def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; def : Pat<(extloadi64i32 addr:$src), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src), x86_subreg_32bit)>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index e55edceff19..aa2fe09b255 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2784,19 +2784,24 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; // extload bool -> extload byte def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; -def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>, - Requires<[In32BitMode]>; +def : Pat<(extloadi16i1 addr:$src), + (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src), + x86_subreg_8bit)>; +def : Pat<(extloadi16i8 addr:$src), + (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src), + x86_subreg_8bit)>; +// For extloads with 32-bit results, chose instructions that +// define the whole 32 bits of the result, to avoid partial-register +// updates. def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; -def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>, - Requires<[In32BitMode]>; def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // anyext -def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>, - Requires<[In32BitMode]>; -def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>, - Requires<[In32BitMode]>; +def : Pat<(i16 (anyext GR8:$src)), + (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; +def : Pat<(i32 (anyext GR8:$src)), + (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; def : Pat<(i32 (anyext GR16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>; |
