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author | Amara Emerson <aemerson@apple.com> | 2019-08-13 06:55:32 +0000 |
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committer | Amara Emerson <aemerson@apple.com> | 2019-08-13 06:55:32 +0000 |
commit | 72c81b94cb3aed05516a872c294899d304e27fc8 (patch) | |
tree | 0e32021b5de374733c9879fd54d435e4ccb36d95 /llvm/lib | |
parent | e14c91b71aedcf494f495189fc0ccae608ecb7fd (diff) | |
download | bcm5719-llvm-72c81b94cb3aed05516a872c294899d304e27fc8.tar.gz bcm5719-llvm-72c81b94cb3aed05516a872c294899d304e27fc8.zip |
[AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcOp. NFC.
llvm-svn: 368653
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 4df68fd1f45..d19e0c1592b 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -2384,13 +2384,14 @@ bool AArch64InstructionSelector::selectTLSGlobalValue( MIB.buildInstr(AArch64::LOADgot, {AArch64::X0}, {}) .addGlobalAddress(&GV, 0, AArch64II::MO_TLS); - Register DestReg = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass); - MIB.buildInstr(AArch64::LDRXui, {DestReg}, {Register(AArch64::X0)}).addImm(0); + auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass}, + {Register(AArch64::X0)}) + .addImm(0); // TLS calls preserve all registers except those that absolutely must be // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be // silly). - MIB.buildInstr(AArch64::BLR, {}, {DestReg}) + MIB.buildInstr(AArch64::BLR, {}, {Load}) .addDef(AArch64::X0, RegState::Implicit) .addRegMask(TRI.getTLSCallPreservedMask()); |