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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2009-04-12 23:00:38 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2009-04-12 23:00:38 +0000 |
| commit | 7186f20a1b8b82d0b90950cdf37fbd8caf84a339 (patch) | |
| tree | 5f459b8eebe830c62747c55f207d040c23eccd2c /llvm/lib | |
| parent | eb4373df60fce72ce24c2df291d9607ce8efb9b1 (diff) | |
| download | bcm5719-llvm-7186f20a1b8b82d0b90950cdf37fbd8caf84a339.tar.gz bcm5719-llvm-7186f20a1b8b82d0b90950cdf37fbd8caf84a339.zip | |
In X86DAGToDAGISel::MatchWrapper, if base or index are set, avoid matching
only if symbolic addresses are RIP relatives.
llvm-svn: 68924
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index f82e9f3514a..bb8061fed8d 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -787,11 +787,16 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { bool is64Bit = Subtarget->is64Bit(); DOUT << "Wrapper: 64bit " << is64Bit; DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n"; + // Under X86-64 non-small code model, GV (and friends) are 64-bits. - // Also, base and index reg must be 0 in order to use rip as base. - if (is64Bit && (TM.getCodeModel() != CodeModel::Small || - AM.Base.Reg.getNode() || AM.IndexReg.getNode())) + if (is64Bit && (TM.getCodeModel() != CodeModel::Small)) + return true; + + // Base and index reg must be 0 in order to use rip as base. + bool canUsePICRel = !AM.Base.Reg.getNode() && !AM.IndexReg.getNode(); + if (is64Bit && !canUsePICRel && TM.symbolicAddressesAreRIPRel()) return true; + if (AM.hasSymbolicDisplacement()) return true; // If value is available in a register both base and index components have |
