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| author | Craig Topper <craig.topper@intel.com> | 2017-12-12 18:39:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-12 18:39:04 +0000 |
| commit | 712a209db9b2f0d88e565d029d1d3f570be91e3e (patch) | |
| tree | b75d88127dddc1a9a0d12572d0d72a37eb833609 /llvm/lib | |
| parent | af7c0ef43577d5b84574437409a61efeb7b92a4e (diff) | |
| download | bcm5719-llvm-712a209db9b2f0d88e565d029d1d3f570be91e3e.tar.gz bcm5719-llvm-712a209db9b2f0d88e565d029d1d3f570be91e3e.zip | |
[X86] Add a couple TODOs about missing coverage/features motivated by D40335
D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code.
llvm-svn: 320507
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index cb98850133a..166a5a9a252 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -7499,6 +7499,8 @@ static SDValue lowerToAddSubOrFMAddSub(const BuildVectorSDNode *BV, // Try to generate X86ISD::FMADDSUB node here. SDValue Opnd2; + // TODO: According to coverage reports, the FMADDSUB transform is not + // triggered by any tests. if (isFMAddSub(Subtarget, DAG, Opnd0, Opnd1, Opnd2)) return DAG.getNode(X86ISD::FMADDSUB, DL, VT, Opnd0, Opnd1, Opnd2); @@ -7844,6 +7846,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { return VectorConstant; BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode()); + // TODO: Support FMSUBADD here if we ever get tests for the FMADDSUB + // transform here. if (SDValue AddSub = lowerToAddSubOrFMAddSub(BV, Subtarget, DAG)) return AddSub; if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG)) |
