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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-16 20:31:50 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-10-16 20:31:50 +0000 |
| commit | 70c82173f3e5215c0eee419dd503eb80f42075f9 (patch) | |
| tree | 9c667e459cdfb5da88ffd57c6f7ee538bd90ec94 /llvm/lib | |
| parent | c659df9389a99ca62a2646da123c198009eb75dc (diff) | |
| download | bcm5719-llvm-70c82173f3e5215c0eee419dd503eb80f42075f9.tar.gz bcm5719-llvm-70c82173f3e5215c0eee419dd503eb80f42075f9.zip | |
R600/SI: Remove unnecessary VALU patterns
These haven't been necessary since allowing
selecting SALU instructions in non-entry blocks
was enabled.
llvm-svn: 219956
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index 097ce59bb6e..a2c3454920f 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1988,48 +1988,12 @@ defm : RsqPat<V_RSQ_F32_e32, f32>; // VOP2 Patterns //===----------------------------------------------------------------------===// -class BinOp64Pat <SDNode node, Instruction inst> : Pat < - (node i64:$src0, i64:$src1), - (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (inst (EXTRACT_SUBREG i64:$src0, sub0), - (EXTRACT_SUBREG i64:$src1, sub0)), sub0), - (inst (EXTRACT_SUBREG i64:$src0, sub1), - (EXTRACT_SUBREG i64:$src1, sub1)), sub1) ->; - -def : BinOp64Pat <and, V_AND_B32_e64>; -def : BinOp64Pat <or, V_OR_B32_e64>; -def : BinOp64Pat <xor, V_XOR_B32_e64>; - -class SextInReg <ValueType vt, int ShiftAmt> : Pat < - (sext_inreg i32:$src0, vt), - (V_ASHRREV_I32_e32 ShiftAmt, (V_LSHLREV_B32_e32 ShiftAmt, $src0)) ->; - -def : SextInReg <i8, 24>; -def : SextInReg <i16, 16>; - def : Pat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; def : Pat < - (i32 (ctpop i32:$popcnt)), - (V_BCNT_U32_B32_e64 $popcnt, 0) ->; - -def : Pat < - (i64 (ctpop i64:$src)), - (INSERT_SUBREG - (INSERT_SUBREG (i64 (IMPLICIT_DEF)), - (V_BCNT_U32_B32_e32 (EXTRACT_SUBREG $src, sub1), - (V_BCNT_U32_B32_e64 (EXTRACT_SUBREG $src, sub0), 0)), - sub0), - (V_MOV_B32_e32 0), sub1) ->; - -def : Pat < (addc i32:$src0, i32:$src1), (V_ADD_I32_e64 $src0, $src1) >; @@ -2600,11 +2564,6 @@ def : IMad24Pat<V_MAD_I32_I24>; def : UMad24Pat<V_MAD_U32_U24>; def : Pat < - (mul i32:$src0, i32:$src1), - (V_MUL_LO_I32 $src0, $src1) ->; - -def : Pat < (mulhu i32:$src0, i32:$src1), (V_MUL_HI_U32 $src0, $src1) >; |
