diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-04 17:06:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-09-04 17:06:53 +0000 |
| commit | 70becc20fa3a957aa78ce52b1a4dc354cf4e460d (patch) | |
| tree | b029b1e8bff25c0009f417a57e999537a89dc749 /llvm/lib | |
| parent | 5afc5a6c1b98f0c93eb1f9902d96e13b58b54a0c (diff) | |
| download | bcm5719-llvm-70becc20fa3a957aa78ce52b1a4dc354cf4e460d.tar.gz bcm5719-llvm-70becc20fa3a957aa78ce52b1a4dc354cf4e460d.zip | |
GlobalISel: Add G_BITREVERSE
This is the first failing pattern for AMDGPU and is trivial to handle.
llvm-svn: 370927
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 00a417fc59e..0a06d8aa172 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1194,6 +1194,8 @@ unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) { break; case Intrinsic::bswap: return TargetOpcode::G_BSWAP; + case Intrinsic::bitreverse: + return TargetOpcode::G_BITREVERSE; case Intrinsic::ceil: return TargetOpcode::G_FCEIL; case Intrinsic::cos: |
