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authorJakob Stoklund Olesen <stoklund@2pi.dk>2009-12-22 18:49:55 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2009-12-22 18:49:55 +0000
commit6f579c12b1d8de460d1aa4af5100d9e909f1428d (patch)
tree36222419f0ae421a246b2285883be2893e043595 /llvm/lib
parentbac37abe732037d8cd118b6e243ead7d35cffd4c (diff)
downloadbcm5719-llvm-6f579c12b1d8de460d1aa4af5100d9e909f1428d.tar.gz
bcm5719-llvm-6f579c12b1d8de460d1aa4af5100d9e909f1428d.zip
Use proper move instructions. Make the verifier happy.
llvm-svn: 91914
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 9b5f79fb10c..7aebdf484f5 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -1373,7 +1373,7 @@ emitPrologue(MachineFunction &MF) const {
// bic r4, r4, MaxAlign
// mov sp, r4
// FIXME: It will be better just to find spare register here.
- BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::R4)
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
.addReg(ARM::SP, RegState::Kill);
AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
TII.get(ARM::t2BICri), ARM::R4)
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