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| author | Chris Lattner <sabre@nondot.org> | 2006-05-06 00:29:37 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-06 00:29:37 +0000 |
| commit | 6d4a2dc4adeec07a1953d5073ea5dff2021225dc (patch) | |
| tree | 42f251e05b1706d16227d03aefb5aea973f4443d /llvm/lib | |
| parent | 86a1467fc0471a2c31fe47f997d93a900318ab43 (diff) | |
| download | bcm5719-llvm-6d4a2dc4adeec07a1953d5073ea5dff2021225dc.tar.gz bcm5719-llvm-6d4a2dc4adeec07a1953d5073ea5dff2021225dc.zip | |
Teach the X86 backend about non-i32 inline asm register classes.
llvm-svn: 28139
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0ec11ac98f6..b771144805e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3998,14 +3998,34 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, default: break; // Unknown constriant letter case 'r': // GENERAL_REGS case 'R': // LEGACY_REGS - return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + if (VT == MVT::i32) + return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0); + else if (VT == MVT::i16) + return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, X86::SP, 0); + else if (VT == MVT::i8) + return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'l': // INDEX_REGS - return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, - X86::ESI, X86::EDI, X86::EBP, 0); + if (VT == MVT::i32) + return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::EBP, 0); + else if (VT == MVT::i16) + return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::BP, 0); + else if (VT == MVT::i8) + return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) case 'Q': // Q_REGS - return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0); + if (VT == MVT::i32) + return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); + else if (VT == MVT::i16) + return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); + else if (VT == MVT::i8) + return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0); + break; case 'x': // SSE_REGS if SSE1 allowed if (Subtarget->hasSSE1()) return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, |
