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| author | Tim Renouf <tim.renouf@amd.com> | 2017-09-11 08:31:32 +0000 |
|---|---|---|
| committer | Tim Renouf <tim.renouf@amd.com> | 2017-09-11 08:31:32 +0000 |
| commit | 6cb007fc728c2d8e2170628b78af4c30e0c5cbdc (patch) | |
| tree | 9caa6f010aa8cc877a977d85ce0992e3cfe93930 /llvm/lib | |
| parent | 12b20f2307a617a35401a28953b9e353321a20cb (diff) | |
| download | bcm5719-llvm-6cb007fc728c2d8e2170628b78af4c30e0c5cbdc.tar.gz bcm5719-llvm-6cb007fc728c2d8e2170628b78af4c30e0c5cbdc.zip | |
AMDGPU: trivial comment change
... to check commit access for new committer.
llvm-svn: 312900
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index b372082868b..029943519c0 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -253,7 +253,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF, if (VGPRIndex == 0) { LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF); if (LaneVGPR == AMDGPU::NoRegister) { - // We have no VGPRs left for spilling SGPRs. Reset because we won't + // We have no VGPRs left for spilling SGPRs. Reset because we will not // partially spill the SGPR to VGPRs. SGPRToVGPRSpills.erase(FI); NumVGPRSpillLanes -= I; |
