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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-10-19 17:31:11 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-10-19 17:31:11 +0000 |
| commit | 6bfc6577f283d4566035bb0dc97d42002b6f2516 (patch) | |
| tree | 0c17105c92c505c15feb4a609696701c7ccd0c10 /llvm/lib | |
| parent | ce3f1915f38f329a867dfb10ed1e82b49d4b52dc (diff) | |
| download | bcm5719-llvm-6bfc6577f283d4566035bb0dc97d42002b6f2516.tar.gz bcm5719-llvm-6bfc6577f283d4566035bb0dc97d42002b6f2516.zip | |
[Hexagon] Remove support for V4
llvm-svn: 344791
Diffstat (limited to 'llvm/lib')
23 files changed, 567 insertions, 757 deletions
diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt index 59377f4f359..3536aa81fb2 100644 --- a/llvm/lib/Target/Hexagon/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/CMakeLists.txt @@ -73,4 +73,3 @@ add_subdirectory(AsmParser) add_subdirectory(Disassembler) add_subdirectory(MCTargetDesc) add_subdirectory(TargetInfo) - diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 69e263a425f..8853dd6d550 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -323,31 +323,27 @@ class Proc<string Name, SchedMachineModel Model, : ProcessorModel<Name, Model, Features>; def : Proc<"generic", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, + [ArchV5, ArchV55, ArchV60, FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; -def : Proc<"hexagonv4", HexagonModelV4, - [ArchV4, - FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, - FeaturePackets, FeatureSmallData]>; -def : Proc<"hexagonv5", HexagonModelV4, - [ArchV4, ArchV5, +def : Proc<"hexagonv5", HexagonModelV5, + [ArchV5, FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv55", HexagonModelV55, - [ArchV4, ArchV5, ArchV55, + [ArchV5, ArchV55, FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, + [ArchV5, ArchV55, ArchV60, FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv62", HexagonModelV62, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, + [ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; def : Proc<"hexagonv65", HexagonModelV65, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, + [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index fccde96d8a3..28965b69e28 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -555,8 +555,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1, if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex)) continue; - // Check that the two instructions are combinable. V4 allows more - // instructions to be merged into a combine. + // Check that the two instructions are combinable. // The order matters because in a A2_tfrsi we might can encode a int8 as // the hi reg operand but only a uint6 as the low reg operand. if ((IsI2LowReg && !areCombinableOperations(TRI, I1, *I2, AllowC64)) || diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h index dc75f8f6340..1bcf4022061 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.h +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -15,7 +15,7 @@ #define HEXAGON_DEP_ARCH_H namespace llvm { namespace Hexagon { -enum class ArchEnum { V4,V5,V55,V60,V62,V65 }; +enum class ArchEnum { NoArch,Generic,V5,V55,V60,V62,V65 }; } // namespace Hexagon } // namespace llvm; #endif // HEXAGON_DEP_ARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.td b/llvm/lib/Target/Hexagon/HexagonDepArch.td index 3594379aa84..ce795692610 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.td +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -18,7 +18,4 @@ def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">; def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">; def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">; -def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "Hexagon::ArchEnum::V4", "Enable Hexagon V4 architecture">; -def HasV4 : Predicate<"HST->hasV4Ops()">, AssemblerPredicate<"ArchV4">; def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">; -def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<"ArchV5">; diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index 5c9ed271cea..0b5efda933d 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -991,7 +991,7 @@ def A2_roundsat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = round($Rss32):sat", -tc_c2f7d806, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_c2f7d806, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -3314,7 +3314,7 @@ def A5_vaddhubs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vaddhub($Rss32,$Rtt32):sat", -tc_2b6f77c6, TypeS_3op>, Enc_d2216a, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_3op>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -4059,7 +4059,7 @@ def F2_conv_d2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_d2df($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4069,7 +4069,7 @@ def F2_conv_d2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_d2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -4081,7 +4081,7 @@ def F2_conv_df2d : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4091,7 +4091,7 @@ def F2_conv_df2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4101,7 +4101,7 @@ def F2_conv_df2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -4113,7 +4113,7 @@ def F2_conv_df2ud : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4123,7 +4123,7 @@ def F2_conv_df2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4133,7 +4133,7 @@ def F2_conv_df2uw : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -4145,7 +4145,7 @@ def F2_conv_df2uw_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000101; let hasNewValue = 1; @@ -4157,7 +4157,7 @@ def F2_conv_df2w : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -4169,7 +4169,7 @@ def F2_conv_df2w_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -4181,7 +4181,7 @@ def F2_conv_sf2d : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4191,7 +4191,7 @@ def F2_conv_sf2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4201,7 +4201,7 @@ def F2_conv_sf2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4211,7 +4211,7 @@ def F2_conv_sf2ud : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4221,7 +4221,7 @@ def F2_conv_sf2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4231,7 +4231,7 @@ def F2_conv_sf2uw : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4243,7 +4243,7 @@ def F2_conv_sf2uw_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4255,7 +4255,7 @@ def F2_conv_sf2w : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4267,7 +4267,7 @@ def F2_conv_sf2w_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32):chop", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4279,7 +4279,7 @@ def F2_conv_ud2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_ud2df($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4289,7 +4289,7 @@ def F2_conv_ud2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_ud2sf($Rss32)", -tc_f3eaa14b, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000001; let hasNewValue = 1; @@ -4301,7 +4301,7 @@ def F2_conv_uw2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_uw2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4311,7 +4311,7 @@ def F2_conv_uw2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_uw2sf($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011001; let hasNewValue = 1; @@ -4323,7 +4323,7 @@ def F2_conv_w2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_w2df($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_3a3d62, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4333,7 +4333,7 @@ def F2_conv_w2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_w2sf($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011010; let hasNewValue = 1; @@ -4345,7 +4345,7 @@ def F2_dfclass : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Pd4 = dfclass($Rss32,#$Ii)", -tc_7a830544, TypeALU64>, Enc_1f19b5, Requires<[HasV5]> { +tc_7a830544, TypeALU64>, Enc_1f19b5 { let Inst{4-2} = 0b100; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b11011100100; @@ -4356,7 +4356,7 @@ def F2_dfcmpeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4368,7 +4368,7 @@ def F2_dfcmpge : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4380,7 +4380,7 @@ def F2_dfcmpgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4392,7 +4392,7 @@ def F2_dfcmpuo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", -tc_1e856f58, TypeALU64>, Enc_fcf7a7, Requires<[HasV5]> { +tc_1e856f58, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4404,7 +4404,7 @@ def F2_dfimm_n : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):neg", -tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> { +tc_234a11a5, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100101; let prefersSlot3 = 1; @@ -4413,7 +4413,7 @@ def F2_dfimm_p : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):pos", -tc_234a11a5, TypeALU64>, Enc_e6c957, Requires<[HasV5]> { +tc_234a11a5, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100100; let prefersSlot3 = 1; @@ -4422,7 +4422,7 @@ def F2_sfadd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfadd($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_6792d5ff, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4436,7 +4436,7 @@ def F2_sfclass : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = sfclass($Rs32,#$Ii)", -tc_7a830544, TypeS_2op>, Enc_83ee64, Requires<[HasV5]> { +tc_7a830544, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101111; @@ -4447,7 +4447,7 @@ def F2_sfcmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.eq($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4459,7 +4459,7 @@ def F2_sfcmpge : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.ge($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4471,7 +4471,7 @@ def F2_sfcmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.gt($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4483,7 +4483,7 @@ def F2_sfcmpuo : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.uo($Rs32,$Rt32)", -tc_1e856f58, TypeS_3op>, Enc_c2b48e, Requires<[HasV5]> { +tc_1e856f58, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4495,7 +4495,7 @@ def F2_sffixupd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupd($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_6792d5ff, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4507,7 +4507,7 @@ def F2_sffixupn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupn($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_6792d5ff, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4519,7 +4519,7 @@ def F2_sffixupr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sffixupr($Rs32)", -tc_f3eaa14b, TypeS_2op>, Enc_5e2823, Requires<[HasV5]> { +tc_f3eaa14b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011101; let hasNewValue = 1; @@ -4530,7 +4530,7 @@ def F2_sffma : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32)", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { +tc_d580173f, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4544,7 +4544,7 @@ def F2_sffma_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32):lib", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { +tc_d580173f, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4558,7 +4558,7 @@ def F2_sffma_sc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", -tc_038a1342, TypeM>, Enc_437f33, Requires<[HasV5]> { +tc_038a1342, TypeM>, Enc_437f33 { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -4572,7 +4572,7 @@ def F2_sffms : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32)", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { +tc_d580173f, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4586,7 +4586,7 @@ def F2_sffms_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32):lib", -tc_d580173f, TypeM>, Enc_2ae154, Requires<[HasV5]> { +tc_d580173f, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4600,7 +4600,7 @@ def F2_sfimm_n : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):neg", -tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> { +tc_234a11a5, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011001; let hasNewValue = 1; @@ -4611,7 +4611,7 @@ def F2_sfimm_p : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):pos", -tc_234a11a5, TypeALU64>, Enc_6c9440, Requires<[HasV5]> { +tc_234a11a5, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011000; let hasNewValue = 1; @@ -4622,7 +4622,7 @@ def F2_sfinvsqrta : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32), "$Rd32,$Pe4 = sfinvsqrta($Rs32)", -tc_4d99bca9, TypeS_2op>, Enc_890909, Requires<[HasV5]> { +tc_4d99bca9, TypeS_2op>, Enc_890909 { let Inst{13-7} = 0b0000000; let Inst{31-21} = 0b10001011111; let hasNewValue = 1; @@ -4634,7 +4634,7 @@ def F2_sfmax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmax($Rs32,$Rt32)", -tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_976ddc4f, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4648,7 +4648,7 @@ def F2_sfmin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmin($Rs32,$Rt32)", -tc_976ddc4f, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_976ddc4f, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4662,7 +4662,7 @@ def F2_sfmpy : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmpy($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_6792d5ff, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011010; @@ -4676,7 +4676,7 @@ def F2_sfrecipa : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", -tc_9c00ce8d, TypeM>, Enc_a94f3b, Requires<[HasV5]> { +tc_9c00ce8d, TypeM>, Enc_a94f3b { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011111; @@ -4689,7 +4689,7 @@ def F2_sfsub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfsub($Rs32,$Rt32)", -tc_6792d5ff, TypeM>, Enc_5ab2be, Requires<[HasV5]> { +tc_6792d5ff, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -16981,7 +16981,7 @@ def M4_cmpyi_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17007,7 +17007,7 @@ def M4_cmpyr_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_8fd5f294, TypeS_3op>, Enc_3d5b28, Requires<[HasV5]> { +tc_8fd5f294, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17360,7 +17360,7 @@ def M5_vdmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", -tc_e913dc32, TypeM>, Enc_88c16c, Requires<[HasV5]> { +tc_e913dc32, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17372,7 +17372,7 @@ def M5_vdmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", -tc_8fd5f294, TypeM>, Enc_a56825, Requires<[HasV5]> { +tc_8fd5f294, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -18207,7 +18207,7 @@ def S2_asr_i_p_rnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii):rnd", -tc_2b6f77c6, TypeS_2op>, Enc_5eac98, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18216,7 +18216,7 @@ def S2_asr_i_p_rnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asrrnd($Rss32,#$Ii)", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op> { let isPseudo = 1; } def S2_asr_i_r : HInst< @@ -25151,7 +25151,7 @@ def S5_asrhub_rnd_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):raw", -tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25164,7 +25164,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25173,7 +25173,7 @@ def S5_asrhub_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):sat", -tc_2b6f77c6, TypeS_2op>, Enc_11a146, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b101; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25186,7 +25186,7 @@ def S5_popcountp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = popcount($Rss32)", -tc_00afc57e, TypeS_2op>, Enc_90cd8b, Requires<[HasV5]> { +tc_00afc57e, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -25197,7 +25197,7 @@ def S5_vasrhrnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):raw", -tc_2b6f77c6, TypeS_2op>, Enc_12b6e9, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000001; @@ -25207,7 +25207,7 @@ def S5_vasrhrnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):rnd", -tc_2b6f77c6, TypeS_2op>, Requires<[HasV5]> { +tc_2b6f77c6, TypeS_2op> { let isPseudo = 1; } def S6_allocframe_to_raw : HInst< @@ -37007,7 +37007,7 @@ def Y5_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "l2fetch($Rs32,$Rtt32)", -tc_daa058fa, TypeST>, Enc_e6abcf, Requires<[HasV5]> { +tc_daa058fa, TypeST>, Enc_e6abcf { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index aad457fc051..f2c27e5e39b 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -1228,7 +1228,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST) : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)), Subtarget(ST) { - bool IsV4 = !Subtarget.hasV5Ops(); auto &HRI = *Subtarget.getRegisterInfo(); setPrefLoopAlignment(4); @@ -1270,10 +1269,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); - if (Subtarget.hasV5Ops()) { - addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); - addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); - } + addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); + addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); // // Handling of scalar operations. @@ -1351,8 +1348,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::CTTZ, MVT::i8, Promote); setOperationAction(ISD::CTTZ, MVT::i16, Promote); - // In V5, popcount can count # of 1s in i64 but returns i32. - // On V4 it will be expanded (set later). + // Popcount can count # of 1s in i64 but returns i32. setOperationAction(ISD::CTPOP, MVT::i8, Promote); setOperationAction(ISD::CTPOP, MVT::i16, Promote); setOperationAction(ISD::CTPOP, MVT::i32, Promote); @@ -1515,57 +1511,28 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::ROTL, MVT::i32, Custom); setOperationAction(ISD::ROTL, MVT::i64, Custom); } - if (Subtarget.hasV5Ops()) { - setOperationAction(ISD::FMA, MVT::f64, Expand); - setOperationAction(ISD::FADD, MVT::f64, Expand); - setOperationAction(ISD::FSUB, MVT::f64, Expand); - setOperationAction(ISD::FMUL, MVT::f64, Expand); - - setOperationAction(ISD::FMINNUM, MVT::f32, Legal); - setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); - - setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); - setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); - setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); - setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); - setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); - setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); - setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); - setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); - setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); - } else { // V4 - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); - setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); - setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); - setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); - setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); - - setOperationAction(ISD::CTPOP, MVT::i8, Expand); - setOperationAction(ISD::CTPOP, MVT::i16, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTPOP, MVT::i64, Expand); - - // Expand these operations for both f32 and f64: - for (unsigned FPExpOpV4 : - {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) { - setOperationAction(FPExpOpV4, MVT::f32, Expand); - setOperationAction(FPExpOpV4, MVT::f64, Expand); - } - for (ISD::CondCode FPExpCCV4 : - {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE, - ISD::SETUO, ISD::SETO}) { - setCondCodeAction(FPExpCCV4, MVT::f32, Expand); - setCondCodeAction(FPExpCCV4, MVT::f64, Expand); - } - } + // V5+. + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FADD, MVT::f64, Expand); + setOperationAction(ISD::FSUB, MVT::f64, Expand); + setOperationAction(ISD::FMUL, MVT::f64, Expand); + + setOperationAction(ISD::FMINNUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); + + setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); + setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); + setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); + setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); + setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); + setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); + setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); + setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); + setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); + setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); + setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); + setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); // Handling of indexed loads/stores: default is "expand". // @@ -1601,42 +1568,18 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti"); setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti"); - if (IsV4) { - // Handle single-precision floating point operations on V4. - if (FastMath) { - setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3"); - setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3"); - setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3"); - setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2"); - setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2"); - // Double-precision compares. - setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2"); - setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2"); - } else { - setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); - setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); - setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3"); - setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2"); - setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2"); - // Double-precision compares. - setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); - setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2"); - } - } - // This is the only fast library function for sqrtd. if (FastMath) setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2"); // Prefix is: nothing for "slow-math", - // "fast2_" for V4 fast-math and V5+ fast-math double-precision + // "fast2_" for V5+ fast-math double-precision // (actually, keep fast-math and fast-math2 separate for now) if (FastMath) { setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3"); setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3"); setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3"); setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3"); - // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok). setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3"); } else { setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); @@ -1646,44 +1589,10 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); } - if (Subtarget.hasV5Ops()) { - if (FastMath) - setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf"); - else - setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf"); - } else { - // V4 - setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf"); - setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf"); - setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf"); - setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf"); - setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf"); - setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf"); - setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf"); - setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf"); - setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi"); - setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi"); - setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); - setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); - setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi"); - setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi"); - setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi"); - setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi"); - setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); - setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2"); - setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2"); - setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2"); - setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2"); - setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2"); - setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2"); - setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2"); - setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2"); - setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2"); - setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2"); - setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2"); - setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); - setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2"); - } + if (FastMath) + setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf"); + else + setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf"); // These cause problems when the shift amount is non-constant. setLibcallName(RTLIB::SHL_I128, nullptr); @@ -3007,7 +2916,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { - return Subtarget.hasV5Ops(); + return true; } /// isLegalAddressingMode - Return true if the addressing mode represented by diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index 1bb3bc1ea31..a1082e7a777 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -194,8 +194,6 @@ class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> : // Instruction Classes Definitions + //===----------------------------------------------------------------------===// -// LD Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. let mayLoad = 1 in class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> @@ -205,9 +203,6 @@ class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; -// ST Instruction Class in V2/V3 can take SLOT0 only. -// ST Instruction Class in V4 can take SLOT0 & SLOT1. -// Definition of the instruction class CHANGED from V2/V3 to V4. let mayStore = 1 in class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> @@ -235,15 +230,6 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Instruction Classes Definitions - //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// V4 Instruction Format Definitions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrFormatsV4.td" - -//===----------------------------------------------------------------------===// -// V60+ Instruction Format Definitions + -//===----------------------------------------------------------------------===// - +include "HexagonInstrFormatsV5.td" include "HexagonInstrFormatsV60.td" include "HexagonInstrFormatsV65.td" diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td index c5fa2599521..482688ab90a 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrFormatsV5.td @@ -1,4 +1,4 @@ -//==- HexagonInstrFormatsV4.td - Hexagon Instruction Formats --*- tablegen -==// +//==- HexagonInstrFormatsV5.td - Hexagon Instruction Formats --*- tablegen -==// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file describes the Hexagon V4 instruction classes in TableGen format. +// This file describes the Hexagon V5 instruction classes in TableGen format. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index b25e316709c..206e74983d2 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1398,7 +1398,5 @@ def: T_R_pat<Y2_dczeroa, int_hexagon_Y2_dczeroa>; def: T_RR_pat<Y4_l2fetch, int_hexagon_Y4_l2fetch>; def: T_RP_pat<Y5_l2fetch, int_hexagon_Y5_l2fetch>; -include "HexagonIntrinsicsV3.td" -include "HexagonIntrinsicsV4.td" include "HexagonIntrinsicsV5.td" include "HexagonIntrinsicsV60.td" diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV3.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV3.td deleted file mode 100644 index 6152cb09882..00000000000 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV3.td +++ /dev/null @@ -1,27 +0,0 @@ -//=- HexagonIntrinsicsV3.td - Target Description for Hexagon -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V3 Compiler Intrinsics in TableGen format. -// -//===----------------------------------------------------------------------===// - -// Vector reduce complex multiply real or imaginary -def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>; -def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>; -def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>; - -// Vector reduce add unsigned halfwords -def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>; - -def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; -def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; -def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; -def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; -def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; -def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td deleted file mode 100644 index 2affe531515..00000000000 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ /dev/null @@ -1,305 +0,0 @@ -//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// This is populated based on the following specs: -// Hexagon V4 Architecture Extensions -// Application-Level Specification -// 80-V9418-12 Rev. A -// June 15, 2010 - -// Vector reduce multiply word by signed half (32x16) -//Rdd=vrmpyweh(Rss,Rtt)[:<<1] -def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>; -def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>; -def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>; - -//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] -def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>; -def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>; -def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>; - -// Vector multiply halfwords, signed by unsigned -// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat -def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>; -def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>; - -// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat -def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>; -def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>; - -// Vector polynomial multiply halfwords -// Rdd=vpmpyh(Rs,Rt) -def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>; -// Rxx[^]=vpmpyh(Rs,Rt) -def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>; - -// Polynomial multiply words -// Rdd=pmpyw(Rs,Rt) -def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>; -// Rxx^=pmpyw(Rs,Rt) -def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>; - -//Rxx^=asr(Rss,Rt) -def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>; -//Rxx^=asl(Rss,Rt) -def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>; -//Rxx^=lsr(Rss,Rt) -def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>; -//Rxx^=lsl(Rss,Rt) -def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>; - -// Multiply and use upper result -def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>; -def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>; -def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>; -def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>; -def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>; - -def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>; -def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>; - -// Vector reduce add unsigned halfwords -def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>; - -def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; -def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; -def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; - -def: T_Q_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>; -def: T_Q_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>; -def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>; - -def : T_Q_PI_pat<A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi>; -def : T_Q_PI_pat<A4_vcmpbgti, int_hexagon_A4_vcmpbgti>; -def : T_Q_PI_pat<A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui>; -def : T_Q_PI_pat<A4_vcmpheqi, int_hexagon_A4_vcmpheqi>; -def : T_Q_PI_pat<A4_vcmphgti, int_hexagon_A4_vcmphgti>; -def : T_Q_PI_pat<A4_vcmphgtui, int_hexagon_A4_vcmphgtui>; -def : T_Q_PI_pat<A4_vcmpweqi, int_hexagon_A4_vcmpweqi>; -def : T_Q_PI_pat<A4_vcmpwgti, int_hexagon_A4_vcmpwgti>; -def : T_Q_PI_pat<A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui>; -def : T_Q_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>; - -def : T_Q_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>; -def : T_Q_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>; -def : T_Q_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>; -def : T_Q_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>; -def : T_Q_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>; -def : T_Q_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>; - -def : T_Q_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>; -def : T_Q_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>; -def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>; - -def : T_Q_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>; -def : T_Q_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>; -def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>; - -def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>; -def : T_Q_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>; - -def : T_RRR_pat <M4_mpyrr_addr, int_hexagon_M4_mpyrr_addr>; -def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>; -def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>; -def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>; -def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>; -def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>; -def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>; - -// Complex multiply 32x16 -def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>; -def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>; - -def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>; -def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>; - -def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>; -def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>; - -// Complex add/sub halfwords/words -def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>; -def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>; -def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>; -def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>; - -def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>; -def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>; - -// Extract bitfield -def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>; -def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>; -def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>; -def : T_RII_pat <S4_extract, int_hexagon_S4_extract>; - -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>; - -// Shift an immediate left by register amount -def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>; - -// Vector reduce maximum halfwords -def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>; -def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>; - -// Vector reduce maximum words -def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>; -def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>; - -// Vector reduce minimum halfwords -def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>; -def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>; - -// Vector reduce minimum words -def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>; -def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>; - -// Rotate and reduce bytes -def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, - u2_0ImmPred:$src3), - (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>; - -// Rotate and reduce bytes with accumulation -// Rxx+=vrcrotate(Rss,Rt,#u2) -def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, - IntRegs:$src3, u2_0ImmPred:$src4), - (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, - IntRegs:$src3, u2_0ImmPred:$src4)>; - -// Vector conditional negate -def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>; - -// Logical xor with xor accumulation -def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>; - -// ALU64 - Vector min/max byte -def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>; -def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>; - -// Shift and add/sub/and/or -def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>; -def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>; -def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>; -def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>; -def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>; -def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>; -def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>; -def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>; - -// Split bitfield -def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>; -def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>; - -def: T_RR_pat<S4_parity, int_hexagon_S4_parity>; - -def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>; -def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>; - -def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>; -def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>; -def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>; - -//******************************************************************* -// ALU32/ALU -//******************************************************************* - -// ALU32 / ALU / Logical Operations. -def: T_RR_pat<A4_andn, int_hexagon_A4_andn>; -def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; - -//******************************************************************* -// ALU32/PERM -//******************************************************************* - -// Combine Words Into Doublewords. -def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>; -def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>; - -//******************************************************************* -// ALU32/PRED -//******************************************************************* - -// Compare -def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>; -def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>; -def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>; - -// Compare To General Register. -def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>; -def: T_Q_RR_pat<C4_cmplte, int_hexagon_C4_cmplte>; -def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>; - -def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>; -def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>; - -def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>; -def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>; - -//******************************************************************* -// CR -//******************************************************************* - -// CR / Logical Operations On Predicates. -def: T_Q_QQQ_pat<C4_and_and, int_hexagon_C4_and_and>; -def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>; -def: T_Q_QQQ_pat<C4_and_or, int_hexagon_C4_and_or>; -def: T_Q_QQQ_pat<C4_and_orn, int_hexagon_C4_and_orn>; -def: T_Q_QQQ_pat<C4_or_and, int_hexagon_C4_or_and>; -def: T_Q_QQQ_pat<C4_or_andn, int_hexagon_C4_or_andn>; -def: T_Q_QQQ_pat<C4_or_or, int_hexagon_C4_or_or>; -def: T_Q_QQQ_pat<C4_or_orn, int_hexagon_C4_or_orn>; - -//******************************************************************* -// XTYPE/ALU -//******************************************************************* - -// Add And Accumulate. - -def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>; -def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>; - - -// XTYPE / ALU / Logical-logical Words. -def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>; -def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>; -def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>; -def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>; -def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>; -def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>; -def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>; -def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>; -def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>; -def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>; -def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>; - -def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>; -def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>; -def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>; - -// Modulo wrap. -def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>; - -// Arithmetic/Convergent round -// Rd=[cround|round](Rs,Rt)[:sat] -// Rd=[cround|round](Rs,#u5)[:sat] -def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>; -def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>; - -def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>; -def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>; - -def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>; -def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>; - -def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>; diff --git a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td index 29f67cffcf8..a852394f216 100644 --- a/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ b/llvm/lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -7,9 +7,314 @@ // //===----------------------------------------------------------------------===// +def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>; +def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>; +def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>; + +// Vector reduce add unsigned halfwords +def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>; + +def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>; +def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>; +def: T_PP_pat<A2_minp, int_hexagon_A2_minp>; +def: T_PP_pat<A2_minup, int_hexagon_A2_minup>; +def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>; +def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>; + +// Vector reduce multiply word by signed half (32x16) +//Rdd=vrmpyweh(Rss,Rtt)[:<<1] +def : T_PP_pat <M4_vrmpyeh_s0, int_hexagon_M4_vrmpyeh_s0>; +def : T_PP_pat <M4_vrmpyeh_s1, int_hexagon_M4_vrmpyeh_s1>; + +//Rdd=vrmpywoh(Rss,Rtt)[:<<1] +def : T_PP_pat <M4_vrmpyoh_s0, int_hexagon_M4_vrmpyoh_s0>; +def : T_PP_pat <M4_vrmpyoh_s1, int_hexagon_M4_vrmpyoh_s1>; + +//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] +def : T_PPP_pat <M4_vrmpyeh_acc_s0, int_hexagon_M4_vrmpyeh_acc_s0>; +def : T_PPP_pat <M4_vrmpyeh_acc_s1, int_hexagon_M4_vrmpyeh_acc_s1>; + +//Rdd=vrmpywoh(Rss,Rtt)[:<<1] +def : T_PPP_pat <M4_vrmpyoh_acc_s0, int_hexagon_M4_vrmpyoh_acc_s0>; +def : T_PPP_pat <M4_vrmpyoh_acc_s1, int_hexagon_M4_vrmpyoh_acc_s1>; + +// Vector multiply halfwords, signed by unsigned +// Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat +def : T_RR_pat <M2_vmpy2su_s0, int_hexagon_M2_vmpy2su_s0>; +def : T_RR_pat <M2_vmpy2su_s1, int_hexagon_M2_vmpy2su_s1>; + +// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat +def : T_PRR_pat <M2_vmac2su_s0, int_hexagon_M2_vmac2su_s0>; +def : T_PRR_pat <M2_vmac2su_s1, int_hexagon_M2_vmac2su_s1>; + +// Vector polynomial multiply halfwords +// Rdd=vpmpyh(Rs,Rt) +def : T_RR_pat <M4_vpmpyh, int_hexagon_M4_vpmpyh>; +// Rxx[^]=vpmpyh(Rs,Rt) +def : T_PRR_pat <M4_vpmpyh_acc, int_hexagon_M4_vpmpyh_acc>; + +// Polynomial multiply words +// Rdd=pmpyw(Rs,Rt) +def : T_RR_pat <M4_pmpyw, int_hexagon_M4_pmpyw>; +// Rxx^=pmpyw(Rs,Rt) +def : T_PRR_pat <M4_pmpyw_acc, int_hexagon_M4_pmpyw_acc>; + +//Rxx^=asr(Rss,Rt) +def : T_PPR_pat <S2_asr_r_p_xor, int_hexagon_S2_asr_r_p_xor>; +//Rxx^=asl(Rss,Rt) +def : T_PPR_pat <S2_asl_r_p_xor, int_hexagon_S2_asl_r_p_xor>; +//Rxx^=lsr(Rss,Rt) +def : T_PPR_pat <S2_lsr_r_p_xor, int_hexagon_S2_lsr_r_p_xor>; +//Rxx^=lsl(Rss,Rt) +def : T_PPR_pat <S2_lsl_r_p_xor, int_hexagon_S2_lsl_r_p_xor>; + +// Multiply and use upper result +def : T_RR_pat <M2_mpysu_up, int_hexagon_M2_mpysu_up>; +def : T_RR_pat <M2_mpy_up_s1, int_hexagon_M2_mpy_up_s1>; +def : T_RR_pat <M2_hmmpyh_s1, int_hexagon_M2_hmmpyh_s1>; +def : T_RR_pat <M2_hmmpyl_s1, int_hexagon_M2_hmmpyl_s1>; +def : T_RR_pat <M2_mpy_up_s1_sat, int_hexagon_M2_mpy_up_s1_sat>; + +def : T_PP_pat <A2_vaddub, int_hexagon_A2_vaddb_map>; +def : T_PP_pat <A2_vsubub, int_hexagon_A2_vsubb_map>; + +// Vector reduce add unsigned halfwords +def : T_PP_pat <M2_vraddh, int_hexagon_M2_vraddh>; + +def: T_P_pat<S2_brevp, int_hexagon_S2_brevp>; +def: T_P_pat<S2_ct0p, int_hexagon_S2_ct0p>; +def: T_P_pat<S2_ct1p, int_hexagon_S2_ct1p>; + +def: T_Q_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>; +def: T_Q_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>; +def: T_Q_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>; + +def : T_Q_PI_pat<A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi>; +def : T_Q_PI_pat<A4_vcmpbgti, int_hexagon_A4_vcmpbgti>; +def : T_Q_PI_pat<A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui>; +def : T_Q_PI_pat<A4_vcmpheqi, int_hexagon_A4_vcmpheqi>; +def : T_Q_PI_pat<A4_vcmphgti, int_hexagon_A4_vcmphgti>; +def : T_Q_PI_pat<A4_vcmphgtui, int_hexagon_A4_vcmphgtui>; +def : T_Q_PI_pat<A4_vcmpweqi, int_hexagon_A4_vcmpweqi>; +def : T_Q_PI_pat<A4_vcmpwgti, int_hexagon_A4_vcmpwgti>; +def : T_Q_PI_pat<A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui>; +def : T_Q_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>; + +def : T_Q_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>; +def : T_Q_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>; +def : T_Q_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>; +def : T_Q_RR_pat<A4_cmpheq, int_hexagon_A4_cmpheq>; +def : T_Q_RR_pat<A4_cmphgt, int_hexagon_A4_cmphgt>; +def : T_Q_RR_pat<A4_cmphgtu, int_hexagon_A4_cmphgtu>; + +def : T_Q_RI_pat<A4_cmpbeqi, int_hexagon_A4_cmpbeqi>; +def : T_Q_RI_pat<A4_cmpbgti, int_hexagon_A4_cmpbgti>; +def : T_Q_RI_pat<A4_cmpbgtui, int_hexagon_A4_cmpbgtui>; + +def : T_Q_RI_pat<A4_cmpheqi, int_hexagon_A4_cmpheqi>; +def : T_Q_RI_pat<A4_cmphgti, int_hexagon_A4_cmphgti>; +def : T_Q_RI_pat<A4_cmphgtui, int_hexagon_A4_cmphgtui>; + +def : T_Q_RP_pat<A4_boundscheck, int_hexagon_A4_boundscheck>; +def : T_Q_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>; + +def : T_RRR_pat <M4_mpyrr_addr, int_hexagon_M4_mpyrr_addr>; +def : T_IRR_pat <M4_mpyrr_addi, int_hexagon_M4_mpyrr_addi>; +def : T_IRI_pat <M4_mpyri_addi, int_hexagon_M4_mpyri_addi>; +def : T_RIR_pat <M4_mpyri_addr_u2, int_hexagon_M4_mpyri_addr_u2>; +def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>; +def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>; +def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>; + +// Complex multiply 32x16 +def : T_PR_pat <M4_cmpyi_wh, int_hexagon_M4_cmpyi_wh>; +def : T_PR_pat <M4_cmpyr_wh, int_hexagon_M4_cmpyr_wh>; + +def : T_PR_pat <M4_cmpyi_whc, int_hexagon_M4_cmpyi_whc>; +def : T_PR_pat <M4_cmpyr_whc, int_hexagon_M4_cmpyr_whc>; + +def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>; +def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>; + +// Complex add/sub halfwords/words +def : T_PP_pat <S4_vxaddsubw, int_hexagon_S4_vxaddsubw>; +def : T_PP_pat <S4_vxsubaddw, int_hexagon_S4_vxsubaddw>; +def : T_PP_pat <S4_vxaddsubh, int_hexagon_S4_vxaddsubh>; +def : T_PP_pat <S4_vxsubaddh, int_hexagon_S4_vxsubaddh>; + +def : T_PP_pat <S4_vxaddsubhr, int_hexagon_S4_vxaddsubhr>; +def : T_PP_pat <S4_vxsubaddhr, int_hexagon_S4_vxsubaddhr>; + +// Extract bitfield +def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>; +def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>; +def : T_PII_pat <S4_extractp, int_hexagon_S4_extractp>; +def : T_RII_pat <S4_extract, int_hexagon_S4_extract>; + +// Vector conditional negate +// Rdd=vcnegh(Rss,Rt) +def : T_PR_pat <S2_vcnegh, int_hexagon_S2_vcnegh>; + +// Shift an immediate left by register amount +def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>; + +// Vector reduce maximum halfwords +def : T_PPR_pat <A4_vrmaxh, int_hexagon_A4_vrmaxh>; +def : T_PPR_pat <A4_vrmaxuh, int_hexagon_A4_vrmaxuh>; + +// Vector reduce maximum words +def : T_PPR_pat <A4_vrmaxw, int_hexagon_A4_vrmaxw>; +def : T_PPR_pat <A4_vrmaxuw, int_hexagon_A4_vrmaxuw>; + +// Vector reduce minimum halfwords +def : T_PPR_pat <A4_vrminh, int_hexagon_A4_vrminh>; +def : T_PPR_pat <A4_vrminuh, int_hexagon_A4_vrminuh>; + +// Vector reduce minimum words +def : T_PPR_pat <A4_vrminw, int_hexagon_A4_vrminw>; +def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>; + +// Rotate and reduce bytes +def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, + u2_0ImmPred:$src3), + (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>; + +// Rotate and reduce bytes with accumulation +// Rxx+=vrcrotate(Rss,Rt,#u2) +def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, + IntRegs:$src3, u2_0ImmPred:$src4), + (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, + IntRegs:$src3, u2_0ImmPred:$src4)>; + +// Vector conditional negate +def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>; + +// Logical xor with xor accumulation +def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>; + +// ALU64 - Vector min/max byte +def : T_PP_pat <A2_vminb, int_hexagon_A2_vminb>; +def : T_PP_pat <A2_vmaxb, int_hexagon_A2_vmaxb>; + +// Shift and add/sub/and/or +def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>; +def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>; +def : T_IRI_pat <S4_addi_asl_ri, int_hexagon_S4_addi_asl_ri>; +def : T_IRI_pat <S4_subi_asl_ri, int_hexagon_S4_subi_asl_ri>; +def : T_IRI_pat <S4_andi_lsr_ri, int_hexagon_S4_andi_lsr_ri>; +def : T_IRI_pat <S4_ori_lsr_ri, int_hexagon_S4_ori_lsr_ri>; +def : T_IRI_pat <S4_addi_lsr_ri, int_hexagon_S4_addi_lsr_ri>; +def : T_IRI_pat <S4_subi_lsr_ri, int_hexagon_S4_subi_lsr_ri>; + +// Split bitfield +def : T_RI_pat <A4_bitspliti, int_hexagon_A4_bitspliti>; +def : T_RR_pat <A4_bitsplit, int_hexagon_A4_bitsplit>; + +def: T_RR_pat<S4_parity, int_hexagon_S4_parity>; + +def: T_Q_RI_pat<S4_ntstbit_i, int_hexagon_S4_ntstbit_i>; +def: T_Q_RR_pat<S4_ntstbit_r, int_hexagon_S4_ntstbit_r>; + +def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>; +def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>; +def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>; + +//******************************************************************* +// ALU32/ALU +//******************************************************************* + +// ALU32 / ALU / Logical Operations. +def: T_RR_pat<A4_andn, int_hexagon_A4_andn>; +def: T_RR_pat<A4_orn, int_hexagon_A4_orn>; + +//******************************************************************* +// ALU32/PERM +//******************************************************************* + +// Combine Words Into Doublewords. +def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>; +def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>; + +//******************************************************************* +// ALU32/PRED +//******************************************************************* + +// Compare +def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>; +def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>; +def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>; + +// Compare To General Register. +def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>; +def: T_Q_RR_pat<C4_cmplte, int_hexagon_C4_cmplte>; +def: T_Q_RR_pat<C4_cmplteu, int_hexagon_C4_cmplteu>; + +def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>; +def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>; + +def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>; +def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>; + +//******************************************************************* +// CR +//******************************************************************* + +// CR / Logical Operations On Predicates. +def: T_Q_QQQ_pat<C4_and_and, int_hexagon_C4_and_and>; +def: T_Q_QQQ_pat<C4_and_andn, int_hexagon_C4_and_andn>; +def: T_Q_QQQ_pat<C4_and_or, int_hexagon_C4_and_or>; +def: T_Q_QQQ_pat<C4_and_orn, int_hexagon_C4_and_orn>; +def: T_Q_QQQ_pat<C4_or_and, int_hexagon_C4_or_and>; +def: T_Q_QQQ_pat<C4_or_andn, int_hexagon_C4_or_andn>; +def: T_Q_QQQ_pat<C4_or_or, int_hexagon_C4_or_or>; +def: T_Q_QQQ_pat<C4_or_orn, int_hexagon_C4_or_orn>; + +//******************************************************************* +// XTYPE/ALU +//******************************************************************* + +// Add And Accumulate. + +def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>; +def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>; + + +// XTYPE / ALU / Logical-logical Words. +def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>; +def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>; +def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>; +def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>; +def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>; +def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>; +def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>; +def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>; +def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>; +def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>; +def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>; + +def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>; +def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>; +def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>; + +// Modulo wrap. +def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>; + +// Arithmetic/Convergent round +// Rd=[cround|round](Rs,Rt)[:sat] +// Rd=[cround|round](Rs,#u5)[:sat] +def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>; +def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>; + +def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>; +def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>; + +def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>; +def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>; + +def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>; + //Rdd[+]=vrmpybsu(Rss,Rtt) //Rdd[+]=vrmpybuu(Rss,Rtt) -let Predicates = [HasV5] in { def : T_PP_pat <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>; def : T_PP_pat <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>; @@ -31,7 +336,6 @@ def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>; // Rd=vaddhub(Rss,Rtt):sat def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>; -} def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>; def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index f671238ec12..ddf5a9ca364 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -365,38 +365,34 @@ def ToI32: OutPatFrag<(ops node:$V), (A2_tfrsi $V)>; // --(2) Type cast ------------------------------------------------------- // -let Predicates = [HasV5] in { - def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; - def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; +def: OpR_R_pat<F2_conv_sf2df, pf1<fpextend>, f64, F32>; +def: OpR_R_pat<F2_conv_df2sf, pf1<fpround>, f32, F64>; - def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; - def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; - def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; - def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; +def: OpR_R_pat<F2_conv_w2sf, pf1<sint_to_fp>, f32, I32>; +def: OpR_R_pat<F2_conv_d2sf, pf1<sint_to_fp>, f32, I64>; +def: OpR_R_pat<F2_conv_w2df, pf1<sint_to_fp>, f64, I32>; +def: OpR_R_pat<F2_conv_d2df, pf1<sint_to_fp>, f64, I64>; - def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; - def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; - def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; - def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; +def: OpR_R_pat<F2_conv_uw2sf, pf1<uint_to_fp>, f32, I32>; +def: OpR_R_pat<F2_conv_ud2sf, pf1<uint_to_fp>, f32, I64>; +def: OpR_R_pat<F2_conv_uw2df, pf1<uint_to_fp>, f64, I32>; +def: OpR_R_pat<F2_conv_ud2df, pf1<uint_to_fp>, f64, I64>; - def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; - def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; - def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; - def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; +def: OpR_R_pat<F2_conv_sf2w_chop, pf1<fp_to_sint>, i32, F32>; +def: OpR_R_pat<F2_conv_df2w_chop, pf1<fp_to_sint>, i32, F64>; +def: OpR_R_pat<F2_conv_sf2d_chop, pf1<fp_to_sint>, i64, F32>; +def: OpR_R_pat<F2_conv_df2d_chop, pf1<fp_to_sint>, i64, F64>; - def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; - def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; - def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; - def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; -} +def: OpR_R_pat<F2_conv_sf2uw_chop, pf1<fp_to_uint>, i32, F32>; +def: OpR_R_pat<F2_conv_df2uw_chop, pf1<fp_to_uint>, i32, F64>; +def: OpR_R_pat<F2_conv_sf2ud_chop, pf1<fp_to_uint>, i64, F32>; +def: OpR_R_pat<F2_conv_df2ud_chop, pf1<fp_to_uint>, i64, F64>; // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp]. -let Predicates = [HasV5] in { - def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; - def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; - def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; - def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; -} +def: Pat<(i32 (bitconvert F32:$v)), (I32:$v)>; +def: Pat<(f32 (bitconvert I32:$v)), (F32:$v)>; +def: Pat<(i64 (bitconvert F64:$v)), (I64:$v)>; +def: Pat<(f64 (bitconvert I64:$v)), (F64:$v)>; multiclass Cast_pat<ValueType Ta, ValueType Tb, RegisterClass RC> { def: Pat<(Tb (bitconvert (Ta RC:$Rs))), (Tb RC:$Rs)>; @@ -599,31 +595,29 @@ def: OpR_RR_pat<A2_vcmpwgtu, RevCmp<setult>, v2i1, V2I32>; def: OpR_RR_pat<A2_vcmpwgtu, setugt, i1, V2I32>; def: OpR_RR_pat<A2_vcmpwgtu, setugt, v2i1, V2I32>; -let Predicates = [HasV5] in { - def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; - def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; - def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; - def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; - def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; - def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; - def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; - def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; - def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; - def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; - def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; - - def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; - def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; - def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; - def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; - def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; - def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; - def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; - def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; - def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; - def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; - def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; -} +def: OpR_RR_pat<F2_sfcmpeq, seteq, i1, F32>; +def: OpR_RR_pat<F2_sfcmpgt, setgt, i1, F32>; +def: OpR_RR_pat<F2_sfcmpge, setge, i1, F32>; +def: OpR_RR_pat<F2_sfcmpeq, setoeq, i1, F32>; +def: OpR_RR_pat<F2_sfcmpgt, setogt, i1, F32>; +def: OpR_RR_pat<F2_sfcmpge, setoge, i1, F32>; +def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setolt>, i1, F32>; +def: OpR_RR_pat<F2_sfcmpge, RevCmp<setole>, i1, F32>; +def: OpR_RR_pat<F2_sfcmpgt, RevCmp<setlt>, i1, F32>; +def: OpR_RR_pat<F2_sfcmpge, RevCmp<setle>, i1, F32>; +def: OpR_RR_pat<F2_sfcmpuo, setuo, i1, F32>; + +def: OpR_RR_pat<F2_dfcmpeq, seteq, i1, F64>; +def: OpR_RR_pat<F2_dfcmpgt, setgt, i1, F64>; +def: OpR_RR_pat<F2_dfcmpge, setge, i1, F64>; +def: OpR_RR_pat<F2_dfcmpeq, setoeq, i1, F64>; +def: OpR_RR_pat<F2_dfcmpgt, setogt, i1, F64>; +def: OpR_RR_pat<F2_dfcmpge, setoge, i1, F64>; +def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setolt>, i1, F64>; +def: OpR_RR_pat<F2_dfcmpge, RevCmp<setole>, i1, F64>; +def: OpR_RR_pat<F2_dfcmpgt, RevCmp<setlt>, i1, F64>; +def: OpR_RR_pat<F2_dfcmpge, RevCmp<setle>, i1, F64>; +def: OpR_RR_pat<F2_dfcmpuo, setuo, i1, F64>; // Avoid C4_cmpneqi, C4_cmpltei, C4_cmplteui, since they cannot form compounds. @@ -746,32 +740,28 @@ class Cmpud<InstHexagon MI>: T3<C2_or, F2_dfcmpuo, MI>; class Cmpufn<InstHexagon MI>: T3<C2_orn, F2_sfcmpuo, MI>; class Cmpudn<InstHexagon MI>: T3<C2_orn, F2_dfcmpuo, MI>; -let Predicates = [HasV5] in { - def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; - def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; - def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; - def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; - def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; - def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; +def: OpmR_RR_pat<Cmpuf<F2_sfcmpeq>, setueq, i1, F32>; +def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, setuge, i1, F32>; +def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, setugt, i1, F32>; +def: OpmR_RR_pat<Cmpuf<F2_sfcmpge>, RevCmp<setule>, i1, F32>; +def: OpmR_RR_pat<Cmpuf<F2_sfcmpgt>, RevCmp<setult>, i1, F32>; +def: OpmR_RR_pat<Cmpufn<F2_sfcmpeq>, setune, i1, F32>; - def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; - def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; - def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; - def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; - def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; - def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; -} +def: OpmR_RR_pat<Cmpud<F2_dfcmpeq>, setueq, i1, F64>; +def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, setuge, i1, F64>; +def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, setugt, i1, F64>; +def: OpmR_RR_pat<Cmpud<F2_dfcmpge>, RevCmp<setule>, i1, F64>; +def: OpmR_RR_pat<Cmpud<F2_dfcmpgt>, RevCmp<setult>, i1, F64>; +def: OpmR_RR_pat<Cmpudn<F2_dfcmpeq>, setune, i1, F64>; -let Predicates = [HasV5] in { - def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; - def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; +def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setone, i1, F32>; +def: OpmR_RR_pat<Outn<F2_sfcmpeq>, setne, i1, F32>; - def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; - def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; +def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setone, i1, F64>; +def: OpmR_RR_pat<Outn<F2_dfcmpeq>, setne, i1, F64>; - def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; - def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; -} +def: OpmR_RR_pat<Outn<F2_sfcmpuo>, seto, i1, F32>; +def: OpmR_RR_pat<Outn<F2_dfcmpuo>, seto, i1, F64>; // --(6) Select ---------------------------------------------------------- @@ -801,27 +791,25 @@ def: Pat<(select I1:$Pu, I64:$Rs, I64:$Rt), (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; -let Predicates = [HasV5] in { - def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), - (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; - def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), - (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; - def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), - (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; - def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), - (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), - (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; +def: Pat<(select I1:$Pu, F32:$Rs, f32ImmPred:$I), + (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; +def: Pat<(select I1:$Pu, f32ImmPred:$I, F32:$Rt), + (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; +def: Pat<(select I1:$Pu, F32:$Rs, F32:$Rt), + (C2_mux I1:$Pu, F32:$Rs, F32:$Rt)>; +def: Pat<(select I1:$Pu, F64:$Rs, F64:$Rt), + (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)), + (C2_mux I1:$Pu, (LoReg $Rs), (LoReg $Rt)))>; - def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), - (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; - def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), - (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; +def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt), + (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>; +def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt), + (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>; - def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), - (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; - def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), - (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; -} +def: Pat<(select (not I1:$Pu), f32ImmPred:$I, F32:$Rs), + (C2_muxir I1:$Pu, F32:$Rs, (ftoi $I))>; +def: Pat<(select (not I1:$Pu), F32:$Rt, f32ImmPred:$I), + (C2_muxri I1:$Pu, (ftoi $I), F32:$Rt)>; def: Pat<(select I1:$Pu, V4I8:$Rs, V4I8:$Rt), (LoReg (C2_vmux I1:$Pu, (ToZext64 $Rs), (ToZext64 $Rt)))>; @@ -889,7 +877,7 @@ let AddedComplexity = 200 in { defm: SelMinMax_pats<setult, I64, A2_minup, A2_maxup>; } -let AddedComplexity = 100, Predicates = [HasV5] in { +let AddedComplexity = 100 in { defm: SelMinMax_pats<setolt, F32, F2_sfmin, F2_sfmax>; defm: SelMinMax_pats<setole, F32, F2_sfmin, F2_sfmax>; defm: SelMinMax_pats<setogt, F32, F2_sfmax, F2_sfmin>; @@ -1014,7 +1002,7 @@ let Predicates = [HasV60] in { def: Pat<(sra (add (sra I32:$Rs, u5_0ImmPred:$u5), 1), (i32 1)), (S2_asr_i_r_rnd I32:$Rs, imm:$u5)>; def: Pat<(sra (add (sra I64:$Rs, u6_0ImmPred:$u6), 1), (i32 1)), - (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>, Requires<[HasV5]>; + (S2_asr_i_p_rnd I64:$Rs, imm:$u6)>; // Prefer S2_addasl_rrri over S2_asl_i_r_acc. let AddedComplexity = 120 in @@ -1191,17 +1179,15 @@ def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>; def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>; def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>; -let Predicates = [HasV5] in { - def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; - def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; +def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>; +def: Pat<(fneg F32:$Rs), (S2_togglebit_i F32:$Rs, 31)>; - def: Pat<(fabs F64:$Rs), - (Combinew (S2_clrbit_i (HiReg $Rs), 31), - (i32 (LoReg $Rs)))>; - def: Pat<(fneg F64:$Rs), - (Combinew (S2_togglebit_i (HiReg $Rs), 31), - (i32 (LoReg $Rs)))>; -} +def: Pat<(fabs F64:$Rs), + (Combinew (S2_clrbit_i (HiReg $Rs), 31), + (i32 (LoReg $Rs)))>; +def: Pat<(fneg F64:$Rs), + (Combinew (S2_togglebit_i (HiReg $Rs), 31), + (i32 (LoReg $Rs)))>; def: Pat<(add I32:$Rs, anyimm:$s16), (A2_addi I32:$Rs, imm:$s16)>; def: Pat<(or I32:$Rs, anyimm:$s10), (A2_orir I32:$Rs, imm:$s10)>; @@ -1267,13 +1253,11 @@ def: OpR_RR_pat<C2_and, Mul, v2i1, V2I1>; def: OpR_RR_pat<C2_and, Mul, v4i1, V4I1>; def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>; -let Predicates = [HasV5] in { - def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; - def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; - def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; - def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; - def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; -} +def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>; +def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>; +def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>; +def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>; +def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>; // In expressions like a0*b0 + a1*b1 + ..., prefer to generate multiply-add, // over add-add with individual multiplies as inputs. @@ -1506,14 +1490,12 @@ def: Pat<(add I32:$Ru, (Su<Mul> I32:$Ry, I32:$Rs)), (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>; -let Predicates = [HasV5] in { - def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), - (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; - def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), - (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; - def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), - (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; -} +def: Pat<(fma F32:$Rs, F32:$Rt, F32:$Rx), + (F2_sffma F32:$Rx, F32:$Rs, F32:$Rt)>; +def: Pat<(fma (fneg F32:$Rs), F32:$Rt, F32:$Rx), + (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; +def: Pat<(fma F32:$Rs, (fneg F32:$Rt), F32:$Rx), + (F2_sffms F32:$Rx, F32:$Rs, F32:$Rt)>; def: Pat<(mul V2I32:$Rs, V2I32:$Rt), @@ -1540,14 +1522,12 @@ def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), // Multiplies two v4i8 vectors. def: Pat<(v4i8 (mul V4I8:$Rs, V4I8:$Rt)), - (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>, - Requires<[HasV5]>; + (S2_vtrunehb (M5_vmpybuu V4I8:$Rs, V4I8:$Rt))>; // Multiplies two v8i8 vectors. def: Pat<(v8i8 (mul V8I8:$Rs, V8I8:$Rt)), (Combinew (S2_vtrunehb (M5_vmpybuu (HiReg $Rs), (HiReg $Rt))), - (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>, - Requires<[HasV5]>; + (S2_vtrunehb (M5_vmpybuu (LoReg $Rs), (LoReg $Rt))))>; // --(10) Bit ------------------------------------------------------------ diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 2e11f875c0f..545def45a1c 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -118,18 +118,7 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { bool HasEHReturn = MF->getInfo<HexagonMachineFunctionInfo>()->hasEHReturn(); - switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) { - case Hexagon::ArchEnum::V4: - case Hexagon::ArchEnum::V5: - case Hexagon::ArchEnum::V55: - case Hexagon::ArchEnum::V60: - case Hexagon::ArchEnum::V62: - case Hexagon::ArchEnum::V65: - return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; - } - - llvm_unreachable("Callee saved registers requested for unknown architecture " - "version"); + return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; } diff --git a/llvm/lib/Target/Hexagon/HexagonSchedule.td b/llvm/lib/Target/Hexagon/HexagonSchedule.td index a1dfb66017a..fa4f9ca639c 100644 --- a/llvm/lib/Target/Hexagon/HexagonSchedule.td +++ b/llvm/lib/Target/Hexagon/HexagonSchedule.td @@ -57,10 +57,10 @@ include "HexagonDepIICScalar.td" include "HexagonDepIICHVX.td" //===----------------------------------------------------------------------===// -// V4 Machine Info + +// V5 Machine Info + //===----------------------------------------------------------------------===// -include "HexagonScheduleV4.td" +include "HexagonScheduleV5.td" // V55 Machine Info + include "HexagonScheduleV55.td" diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/llvm/lib/Target/Hexagon/HexagonScheduleV5.td index 69b704a805b..9a893f6dde0 100644 --- a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/llvm/lib/Target/Hexagon/HexagonScheduleV5.td @@ -1,4 +1,4 @@ -//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// +//=-HexagonScheduleV5.td - HexagonV5 Scheduling Definitions --*- tablegen -*-=// // // The LLVM Compiler Infrastructure // @@ -10,8 +10,8 @@ def LD_tc_ld_SLOT01 : InstrItinClass; def ST_tc_st_SLOT01 : InstrItinClass; -class HexagonV4PseudoItin { - list<InstrItinData> V4PseudoItin_list = [ +class HexagonV5PseudoItin { + list<InstrItinData> V5PseudoItin_list = [ InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [SLOT2, SLOT3]>]>, @@ -20,27 +20,27 @@ class HexagonV4PseudoItin { ]; } -def HexagonV4ItinList : DepScalarItinV4, HexagonV4PseudoItin { - list<InstrItinData> V4Itin_list = [ +def HexagonV5ItinList : DepScalarItinV5, HexagonV5PseudoItin { + list<InstrItinData> V5Itin_list = [ InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>, InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]> ]; list<InstrItinData> ItinList = - !listconcat(V4Itin_list, DepScalarItinV4_list, V4PseudoItin_list); + !listconcat(V5Itin_list, DepScalarItinV5_list, V5PseudoItin_list); } -def HexagonItinerariesV4 : +def HexagonItinerariesV5 : ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], - [Hex_FWD], HexagonV4ItinList.ItinList>; + [Hex_FWD], HexagonV5ItinList.ItinList>; -def HexagonModelV4 : SchedMachineModel { +def HexagonModelV5 : SchedMachineModel { // Max issue per cycle == bundle width. let IssueWidth = 4; - let Itineraries = HexagonItinerariesV4; + let Itineraries = HexagonItinerariesV5; let LoadLatency = 1; let CompleteModel = 0; } //===----------------------------------------------------------------------===// -// Hexagon V4 Resource Definitions - +// Hexagon V5 Resource Definitions - //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 0686d6eb611..68e276be0f6 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -93,7 +93,6 @@ HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { static std::map<StringRef, Hexagon::ArchEnum> CpuTable{ {"generic", Hexagon::ArchEnum::V60}, - {"hexagonv4", Hexagon::ArchEnum::V4}, {"hexagonv5", Hexagon::ArchEnum::V5}, {"hexagonv55", Hexagon::ArchEnum::V55}, {"hexagonv60", Hexagon::ArchEnum::V60}, diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index dc8d173a505..eaae4db6ba9 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -59,7 +59,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { public: Hexagon::ArchEnum HexagonArchVersion; - Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4; + Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::NoArch; CodeGenOpt::Level OptLevel; /// True if the target should use Back-Skip-Back scheduling. This is the /// default for V60. @@ -158,7 +158,9 @@ public: bool useNewValueStores() const { return UseNewValueStores; } bool useSmallData() const { return UseSmallData; } - bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } + bool useHVXOps() const { + return HexagonHVXVersion > Hexagon::ArchEnum::NoArch; + } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index a896700df1b..93b5bedbb38 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -768,7 +768,7 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI, // Make sure that for non-POST_INC stores: // 1. The only use of reg is DepReg and no other registers. - // This handles V4 base+index registers. + // This handles base+index registers. // The following store can not be dot new. // Eg. r0 = add(r0, #3) // memw(r1+r0<<#2) = r0 @@ -838,11 +838,7 @@ static bool isImplicitDependency(const MachineInstr &I, bool CheckDef, return false; } -// Check to see if an instruction can be dot new -// There are three kinds. -// 1. dot new on predicate - V2/V3/V4 -// 2. dot new on stores NV/ST - V4 -// 3. dot new on jump NV/J - V4 -- This is generated in a pass. +// Check to see if an instruction can be dot new. bool HexagonPacketizerList::canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII, const TargetRegisterClass* RC) { @@ -1075,9 +1071,6 @@ bool HexagonPacketizerList::isSoloInstruction(const MachineInstr &MI) { if (MI.isInlineAsm() && !ScheduleInlineAsm) return true; - // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints: - // trap, pause, barrier, icinva, isync, and syncht are solo instructions. - // They must not be grouped with other instructions in a packet. if (isSchedBarrier(MI)) return true; @@ -1289,8 +1282,8 @@ bool HexagonPacketizerList::hasRegMaskDependence(const MachineInstr &I, return false; } -bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I, - const MachineInstr &J) { +bool HexagonPacketizerList::hasDualStoreDependence(const MachineInstr &I, + const MachineInstr &J) { bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J); bool StoreI = I.mayStore(), StoreJ = J.mayStore(); if ((SysI && StoreJ) || (SysJ && StoreI)) @@ -1343,10 +1336,10 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { if (Dependence) return false; - // V4 allows dual stores. It does not allow second store, if the first - // store is not in SLOT0. New value store, new value jump, dealloc_return - // and memop always take SLOT0. Arch spec 3.4.4.2. - Dependence = hasV4SpecificDependence(I, J); + // Dual-store does not allow second store, if the first store is not + // in SLOT0. New value store, new value jump, dealloc_return and memop + // always take SLOT0. Arch spec 3.4.4.2. + Dependence = hasDualStoreDependence(I, J); if (Dependence) return false; @@ -1505,10 +1498,10 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { } // For Order dependences: - // 1. On V4 or later, volatile loads/stores can be packetized together, - // unless other rules prevent is. + // 1. Volatile loads/stores can be packetized together, unless other + // rules prevent is. // 2. Store followed by a load is not allowed. - // 3. Store followed by a store is only valid on V4 or later. + // 3. Store followed by a store is valid. // 4. Load followed by any memory operation is allowed. if (DepType == SDep::Order) { if (!PacketizeVolatiles) { @@ -1555,7 +1548,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { continue; } - // For V4, special case ALLOCFRAME. Even though there is dependency + // Special case for ALLOCFRAME: even though there is dependency // between ALLOCFRAME and subsequent store, allow it to be packetized // in a same packet. This implies that the store is using the caller's // SP. Hence, offset needs to be updated accordingly. diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h index d54dd7050e1..ca70cf967a4 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -149,7 +149,7 @@ protected: bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); - bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J); + bool hasDualStoreDependence(const MachineInstr &I, const MachineInstr &J); bool producesStall(const MachineInstr &MI); }; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index b208a366812..c707dcb0316 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -634,8 +634,7 @@ bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII, return false; } - if (STI.getCPU().equals_lower("hexagonv4") || - STI.getCPU().equals_lower("hexagonv5") || + if (STI.getCPU().equals_lower("hexagonv5") || STI.getCPU().equals_lower("hexagonv55") || STI.getCPU().equals_lower("hexagonv60")) { // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index b211a81524f..8f3c09e7204 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -61,8 +61,6 @@ cl::opt<bool> llvm::HexagonDisableDuplex cl::desc("Disable looking for duplex instructions for Hexagon")); namespace { // These flags are to be deprecated -cl::opt<bool> MV4("mv4", cl::Hidden, cl::desc("Build for Hexagon V4"), - cl::init(false)); cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"), cl::init(false)); cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"), @@ -83,18 +81,18 @@ cl::opt<Hexagon::ArchEnum> clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), // Sentinal for no value specified - clEnumValN(Hexagon::ArchEnum::V5, "", "")), + clEnumValN(Hexagon::ArchEnum::Generic, "", "")), // Sentinal for flag not present - cl::init(Hexagon::ArchEnum::V4), cl::ValueOptional); + cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional); + static cl::opt<bool> - DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions")); + DisableHVX("mno-hvx", cl::Hidden, + cl::desc("Disable Hexagon Vector eXtensions")); static StringRef DefaultArch = "hexagonv60"; static StringRef HexagonGetArchVariant() { - if (MV4) - return "hexagonv4"; if (MV5) return "hexagonv5"; if (MV55) @@ -123,7 +121,7 @@ StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) { return ArchV; } -unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV4FU::SLOT3; } +unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; } namespace { @@ -279,6 +277,7 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { Result.push_back(FS); switch (EnableHVX) { + case Hexagon::ArchEnum::V5: case Hexagon::ArchEnum::V55: break; case Hexagon::ArchEnum::V60: @@ -290,14 +289,14 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { case Hexagon::ArchEnum::V65: Result.push_back("+hvxv65"); break; - case Hexagon::ArchEnum::V5:{ + case Hexagon::ArchEnum::Generic:{ Result.push_back(StringSwitch<StringRef>(CPU) .Case("hexagonv60", "+hvxv60") .Case("hexagonv62", "+hvxv62") .Case("hexagonv65", "+hvxv65")); break; } - case Hexagon::ArchEnum::V4: + case Hexagon::ArchEnum::NoArch: // Sentinal if -mhvx isn't specified break; } @@ -307,15 +306,9 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { static bool isCPUValid(std::string CPU) { - std::vector<std::string> table - { - "generic", - "hexagonv4", - "hexagonv5", - "hexagonv55", - "hexagonv60", - "hexagonv62", - "hexagonv65", + std::vector<std::string> table { + "generic", "hexagonv5", "hexagonv55", "hexagonv60", + "hexagonv62", "hexagonv65", }; return std::find(table.begin(), table.end(), CPU) != table.end(); @@ -336,8 +329,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // Make sure that +hvx-length turns hvx on, and that "hvx" alone // turns on hvxvNN, corresponding to the existing ArchVNN. FeatureBitset FB = S; - unsigned CpuArch = ArchV4; - for (unsigned F : {ArchV65, ArchV62, ArchV60, ArchV55, ArchV5, ArchV4}) { + unsigned CpuArch = ArchV5; + for (unsigned F : {ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) { if (!FB.test(F)) continue; CpuArch = F; @@ -402,7 +395,6 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { static std::map<StringRef,unsigned> ElfFlags = { - {"hexagonv4", ELF::EF_HEXAGON_MACH_V4}, {"hexagonv5", ELF::EF_HEXAGON_MACH_V5}, {"hexagonv55", ELF::EF_HEXAGON_MACH_V55}, {"hexagonv60", ELF::EF_HEXAGON_MACH_V60}, |
