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| author | Eugene Leviant <eleviant@accesssoftek.com> | 2017-11-21 11:01:28 +0000 |
|---|---|---|
| committer | Eugene Leviant <eleviant@accesssoftek.com> | 2017-11-21 11:01:28 +0000 |
| commit | 6bc35a93e6be166ec25cc42ab081ea161740ba3b (patch) | |
| tree | dd47eed5f215d3bf5f551553d3e940621c9dd306 /llvm/lib | |
| parent | 5c7fe5df5312d02c027531a9121e7ac9e8e01b73 (diff) | |
| download | bcm5719-llvm-6bc35a93e6be166ec25cc42ab081ea161740ba3b.tar.gz bcm5719-llvm-6bc35a93e6be166ec25cc42ab081ea161740ba3b.zip | |
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
llvm-svn: 318749
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA57.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td index 525079d12d5..1ed9e14dfcd 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA57.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57.td @@ -971,9 +971,9 @@ def : InstRW<[A57WriteVABAL, A57ReadVABAL], (instregex "VABAL(s|u)")>; def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>; // ASIMD arith, basic -def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW", +def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW", "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)", - "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>; + "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>; // ASIMD arith, complex def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB", |
