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| author | David Green <david.green@arm.com> | 2019-11-04 13:33:22 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-11-04 13:37:01 +0000 |
| commit | 6bae5d16a28662fee78595e827343ce1c575b1de (patch) | |
| tree | 9af6439d655d719a851f648bffa1e12d896ab3a1 /llvm/lib | |
| parent | 659bd73d13686948c2b4dbee02df2f82542849dd (diff) | |
| download | bcm5719-llvm-6bae5d16a28662fee78595e827343ce1c575b1de.tar.gz bcm5719-llvm-6bae5d16a28662fee78595e827343ce1c575b1de.zip | |
[ARM] Add vrev32 NEON fp16 patterns
Fill in the gaps for vrev32.16 f16 patterns, extending the existing i16
patterns.
Differential Revision: https://reviews.llvm.org/D69508
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 60ca92e5804..94bb45bde57 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -6797,9 +6797,12 @@ def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; let Predicates = [HasNEON] in { -def : Pat<(v4f32 (ARMvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; -def : Pat<(v8f16 (ARMvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>; -def : Pat<(v4f16 (ARMvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>; + def : Pat<(v4f32 (ARMvrev64 (v4f32 QPR:$Vm))), + (VREV64q32 QPR:$Vm)>; + def : Pat<(v8f16 (ARMvrev64 (v8f16 QPR:$Vm))), + (VREV64q16 QPR:$Vm)>; + def : Pat<(v4f16 (ARMvrev64 (v4f16 DPR:$Vm))), + (VREV64d16 DPR:$Vm)>; } // VREV32 : Vector Reverse elements within 32-bit words @@ -6821,6 +6824,13 @@ def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>; def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>; def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>; +let Predicates = [HasNEON] in { + def : Pat<(v8f16 (ARMvrev32 (v8f16 QPR:$Vm))), + (VREV32q16 QPR:$Vm)>; + def : Pat<(v4f16 (ARMvrev32 (v4f16 DPR:$Vm))), + (VREV32d16 DPR:$Vm)>; +} + // VREV16 : Vector Reverse elements within 16-bit halfwords class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
